L6364 datasheet(7/60 Pages) STMICROELECTRONICS

7 / 60 page

Symbol

Parameter

Min.

Typ.

Max.

Unit

VSUP

VPLUS supply voltage, IV5V0= 50 mA, (DC-DC disabled)

Minimum VPLUS (DC-DC enabled) (see Figure 15)

10.5

VDCDC_5V_MIN

Minimum VDCDC output voltage (VSET) for use of V5V

6.1

CBLK

Blocking capacitor on VPLUS

100

CEMC

EMC blocking capacitor

470

CV3V3

Capacitor CV3V3

μF

CV5V

Capacitor CV5V (V5V in use)

μF

CDOUT

Capacitor CDOUT

0.01

μF

CDCDC

Capacitor CDCDC

2.2

LDCDC

Inductor LDCDC

220

CQLOAD_MAX

Maximum load capacitor CQ (see Figure 21)(1)

250

CDIOLOAD_MAX

Maximum load capacitor DIO (see Figure 21) (1)

250

CJOINLOAD_MAX

Maximum load capacitor JOIN mode (see Figure 22) (1)

500

LCQLOAD_MAX

Maximum load inductance CQ (see Figure 21)

(2)

LDIOLOAD_MAX

Maximum load inductance DIO (see Figure 21)

(2)

LJOINLOAD_MAX

Maximum load inductance JOIN mode (see Figure 22)

(2)

1. values measured with pure capacitive load.

2. unlimited, see Section 19 for further details.

4.4

Electrical Characteristics

Electrical parameters are valid over the operating temperature and voltage range, unless otherwise stated.

Table 5. Receiver CQ/DIO

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

VTHH

Input threshold “H”

RF bit = 0 in

CFG register (see

Table 32. Register

map ).

10.5

VTHL

Input threshold “L”

11.5

VTHHR

Input threshold “H”

RF bit = 1 in

CFG register (see

Table 32. Register

map ).

-10%

(VVPLUS/1.8)-0.5

+10%

VTHLR

Input threshold “L”

-10%

(VVPLUS/1.8)+0.5

+10%

VHYS

Hysteresis

0.5

1.5

VIN

Input range CQ/DIO

VVPLUS +10

fBIT

Data rate

BD bit = 0 in

CFG register (see

Table 32. Register

map ).

38.4

kBaud

BD bit = 1 in

CFG register (see

Table 32. Register

map ).

230.4

kBaud

TBIT

Bit time

1/fBIT

μs

L6364

Electrical Characteristics

DS13363 - Rev 4

page 7/60

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