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SH79F6488P/080PR bảng dữ liệu(PDF) 91 Page - SINOWEALTH Electronic Ltd |
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SH79F6488P/080PR bảng dữ liệu(HTML) 91 Page - SINOWEALTH Electronic Ltd |
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91 / 152 page  SH79F6488/SH79F6489 91 Table 8.17 PWM Duty Control Register (PWM0DH/L) DAH, D9H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM0DH (DAH) - - - - PWM0D.11 PWM0D.10 PWM0D.9 PWM0D.8 PWM0DL (D9H) PWM0D.7 PWM0D.6 PWM0D.5 PWM0D.4 PWM0D.3 PWM0D.2 PWM0D.1 PWM0D.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 11-0 PWM0D[11:0] 12-bit PWM duty registers If PWM0P ≤ PWM0D, PWM0 outputs high level when the PWM0S bit is set to “0”. PWM0 outputs GND level when the PWM0S bit is set to “1”. If PWM0D = 00H, PWM0 outputs GND level when the PWM0S bit is set to “0”. PWM0 outputs high level when the PWM0S bit is set to “1”. Table 8.18 PWM Duty Control Register( PWM1DH/L) DCH, DBH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM1DH (DCH) - - - - PWM1D.11 PWM1D.10 PWM1D.9 PWM1D.8 PWM1DL (DBH) PWM1D.7 PWM1D.6 PWM1D.5 PWM1D.4 PWM1D.3 PWM1D.2 PWM1D.1 PWM1D.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 11-0 PWM1D[11:0] 12-bit PWM duty registers If PWM1P ≤ PWM1D, PWM1 outputs high level when the PWM1S bit is set to “0”. PWM1 outputs GND level when the PWM1S bit is set to “1”. If PWM1D = 00H, PWM1 outputs GND level when the PWM1S bit is set to “0”. PWM1 outputs high level when the PWM1S bit is set to “1”. Table 8.19 PWM Duty Control Register (PWM2DH/L) DEH, DDH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM2DH (DEH) - - - - PWM2D.11 PWM2D.10 PWM2D.9 PWM2D.8 PWM2DL (DDH) PWM2D.7 PWM2D.6 PWM2D.5 PWM2D.4 PWM2D.3 PWM2D.2 PWM2D.1 PWM2D.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 11-0 PWM2D[11:0] 12-bit PWM duty registers If PWM2P ≤ PWM2D, PWM2 outputs high level when the PWM2S bit is set to “0”. PWM2 outputs GND level when the PWM2S bit is set to “1”. If PWM2D = 00H, PWM2 outputs GND level when the PWM2S bit is set to “0”. PWM2 outputs high level when the PWM2S bit is set to “1”. Note: The change of PWMxDH will take affect at the next PWMx period. The user must change PWMxDL at first, and then change PWMxDH for changing PWMx duty. |
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