SH79F6488PSLASH080PR datasheet(59/152 Pages) SINOWEALTH

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SH79F6488/SH79F6489

7.8.4 Timer4

Timer4 is a 16-bit auto-reload timer. It is implemented as a 16-bit register accessed as two cascaded data registers: TH4 and

TL4. It is controlled by the T4CON register. The Timer 4 interrupt can be enabled by setting ET4 bit in IEN0 register (Refer to

interrupt Section for details).

When writing to TH4 and TL4, they are used as timer load register. When reading from TH4 and TL4, they are used as timer

counter register. Setting the TR4 bit enables Timer 4 to count up. The timer will overflow from 0xFFFF to 0x0000 and set the

TF4 bit. This overflow also causes the 16-bit value written in timer load register to be reloaded into the timer counter register.

Writing to TH4 also can cause the 16-bit value written in timer load register to be reloaded into the timer counter register.

Read or write operation to TH4 and TL4 should follow these steps:

Write operation:Low nibble first,High nibble to update the counter.

Read operation:High nibble first,Low nibble followed.

Timer4 Modes

Timer4 has three operating modes: 16-bit auto-reload counter/timer, Baud Rate Generator and 16-bit auto-reload timer with T4

edge trig. These modes are selected by T4M[1:0] bits in T4CON Register.

Mode0: 16-bit Auto-Reload Counter/Timer

Timer4 operates as 16-bit counter/timer in Mode 0. The TH4 register holds the high eight bits of the 16-bit counter/timer, TL4

holds the low eight bits. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the timer overflow flag

TF4 (T4CON.7) is set and the 16-bit value in timer load register are reloaded into timer counter register, and an interrupt will

occur if Timer 4 interrupts is enabled. The T4CLKS bit (T4CON.0) selects the counter/timer's clock source.

If T4CLKS = 1, external clock from the Pin T4 is selected as Timer4 clock, after prescaled, it will increase the Counter/Timer4

Data register. Else if T4CLKS = 0, the system clock is selected as Timer4 clock.

Setting the TR4 bit (T4CON.1) enables the timer. Setting TR4 does not force the timer to reset. The timer load register should

be loaded with the desired initial value before the timer is enabled.

In Compare mode, the T4 pin is automatically set as output mode by hardware. the internal counter is constantly countered

from TH4 and TL4 register value to 0xFFFF. When an overflow occurs, the T4 pin will be inverted. At the same time, interrupt

flag bit of Time4 is set. Timer4 must be running in Timer mode (T4CLKS = 0) when compare function enabled.

TF4

T4CLKS

The Block Diagram of Mode 0 of Timer 4

TL4

TH4

Increment Mode

0:Switch Off

1:Switch On

16 bit Counter

Interrupt

Request

Overflow

Flag

TR4

System Clock

Prescaler

1,8,64,256

T4PS[1:0]

T4CLKS=0

TC4=1

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