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SH79F6488P/080PR bảng dữ liệu(PDF) 84 Page - SINOWEALTH Electronic Ltd |
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SH79F6488P/080PR bảng dữ liệu(HTML) 84 Page - SINOWEALTH Electronic Ltd |
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84 / 152 page ![]() SH79F6488/SH79F6489 84 Slave Mode (1) Enable The SPI operates in slave mode when the MSTR is cleared in the SPCON register. Before a data transmission occurs, the slave select (SS ——— ) pin of the Slave device must be set to ’0’. The SS ——— pin must remain low until the 1-byte transmission is complete. (2) Transmit & Receive When in SPI slave mode, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter counts SCK edges. When 8 bits have been shifted in the receive shift register and another 8 bits have been shifted out the transmit shift register, the SPIF flag is set to logic ‘1’. Data is read from the receive shift register by reading SPDAT. If interrupts are enabled, an interrupt request is generated when the SPIF flag is set. To prevent an overflow condition, the SPI slave software must clear the SPIF bit in SPSTA register before another byte enters the receive shift register. Else a RXOV signal will be set to indicate data over-run occurs, and the receive shift register keep the byte that SPIF was lastly set, also the SPI slave will not receive any further data until SPIF was cleared. A SPI slave cannot initiate transfers. Data to be transferred to the master device is pre-loaded into the shift register by writing to SPDAT. Writes to SPDAT are placed in the transmit buffer first. So a SPI slave must complete the write to the SPDAT (transmit shift register) in one SPI clock before the master starts a new transmission. If the write to SPDAT is late in the first transmission, the SPI slave will transmit a ‘0x00’ byte in the following transmission. if the write operation occurs during this time, a WCOL signal will be set. If the transmit shift register already contains data, the SPI slave will generate a WCOL signal to indicate writing too fast. But the data in transmit shift register will not be affected, and the transmission continues uninterrupted. |
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