SH32F2601PSLASH032PR datasheet(57/370 Pages) SINOWEALTH

57 / 370 page

SH32F2601

10.3.1

Clock Control Register (RCC_CR)

Offset Address: 0x0000

Reset Value:

0x0000 0000

b31

b30

b29

b28

b27

b26

b25

b24

b23

b22

b21

b20

b19

b18

b17

b16

Reserved

b15

b14

b13

b12

b11

b10

Reserved

CSM

PLL

RDY

PLL

HSE

RDY

HSE

SWS[1:0]

SW[1:0]

Bit

Symbol

Description

31 ~ 9

Reserved

CSMON

CSM Clock detection Enable Bit

0: CSM Disable

1: CSM Enable

PLLRDY

PLL clock ready flag

After the PLL is locked, it is set to '1' by hardware.

0: PLL is not locked

1: PLL is locked

PLLON

PLL enable

Set to '1' by software or cleared to enable or disable PLL

This bit cannot be cleared when PLL clock is used as the system clock.

0: PLL is disabled

1: PLL is enabled

HSERDY

External high frequency oscillator ready flag

Set to 1 by hardware to indicate that the external high frequency oscillator is

stabilized.After the HSEON bit is cleared, this bit requires 6 external 4-12MHz

clock cycles to be cleared.

0: External 4-12MHz clock is not ready

1: External 4-12MHz clock is ready

Description: This bit is dependent on HSEON and only indicates the external

high frequency oscillator ready state.

HSEON

External high frequency oscillator enable

Set to 1 or cleared by software. This bit cannot be cleared when the HSE is

used directly or indirectly as the system clock.

0: HSE oscillator is disabled

1: HSE oscillator is enabled

3 ~ 2

SWS[1:0]

System clock switch status

Set to ‘1’ or cleared by hardware to indicate the system clock source.

00: HSI as the system clock

01: HSE as the system clock

1x: PLL output as system clock

1 ~ 0

SW[1:0]

System clock switch

Set to ‘1’ or cleared by software to select the system clock source.

00: HSI as the system clock

01: HSE as the system clock

1x: PLL output as system clock

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