ADF4252

Data Sheet

Rev. E | Page 2 of 30

TABLE OF CONTENTS

Features .............................................................................................. 1

 

Applications....................................................................................... 1

 

General Description ......................................................................... 1

 

Functional Block Diagram .............................................................. 1

 

Revision History ............................................................................... 3

 

Specifications..................................................................................... 4

 

Timing Characteristics ................................................................ 5

 

Absolute Maximum Ratings............................................................ 6

 

ESD Caution.................................................................................. 6

 

Pin Configuration and Function Descriptions............................. 7

 

Typical Performance Characteristics ............................................. 8

 

Detailed Functional Block Diagram ............................................ 12

 

Theory of Operation ...................................................................... 13

 

Reference Input Section............................................................. 13

 

RF and IF Input Stage ................................................................ 13

 

RF INT Divider........................................................................... 13

 

INT, FRAC, MOD, and R Relationship ................................... 13

 

RF R Counter .............................................................................. 13

 

IF R Counter ............................................................................... 13

 

IF Prescaler (P/P + 1)................................................................. 14

 

IF A and B Counters .................................................................. 14

 

Pulse Swallow Function............................................................. 14

 

Phase Frequency Detector (PFD) and Charge Pump............ 14

 

MUXOUT and Lock Detect...................................................... 14

 

Lock Detect ................................................................................. 14

 

Input Shift Register..................................................................... 14

 

Register Maps .................................................................................. 15

 

Register Descriptions ..................................................................... 23

 

RF N Divider Register (Address R0) ....................................... 23

 

RF R Divider Register (Address R1) ........................................ 23

 

RF Control Register (Address R2) ........................................... 23

 

Master Register (Address R3) ................................................... 24

 

IF N Divider Register (Address R4)......................................... 24

 

IF R Divider Register (Address R5) ......................................... 25

 

IF Control Register (Address R6)............................................. 25

 

Device Programming after Initial Power-Up.............................. 26

 

RF and IF Synthesizers Operational ........................................ 26

 

RF Synthesizer Operational, IF Power-Down .......................... 26

 

IF Synthesizer Operational, RF Power-Down .......................... 26

 

RF Synthesizer: An Example..................................................... 26

 

IF Synthesizer: An Example...................................................... 26

 

Modulus....................................................................................... 26

 

Reference Doubler and Reference Divider ............................. 26

 

12-Bit Programmable Modulus................................................ 26

 

Spurious Optimization and Fastlock ....................................... 27

 

Spurious Signals—Predicting Where They Appear............... 27

 

Prescaler....................................................................................... 27

 

Filter Design—ADIsimPLL....................................................... 27

 

Interfacing ....................................................................................... 28

 

ADuC812 Interface .................................................................... 28

 

ADSP-2181 Interface ................................................................. 28

 

PCB Design Guidelines for Chip Scale Package......................... 29

 

Outline Dimensions ....................................................................... 30

 

Ordering Guide .......................................................................... 30