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STM32WB10CC bảng dữ liệu(PDF) 27 Page - STMicroelectronics |
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STM32WB10CC bảng dữ liệu(HTML) 27 Page - STMicroelectronics |
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27 / 110 page ![]() DS13259 Rev 2 27/110 STM32WB10CC Functional overview 43 1. Legend: Y = Yes (enabled). O = Optional (disabled by default, can be enabled by software). R = data retained. - = Not available. Gray cells indicate Wakeup capability. 2. The SRAM clock can be gated on or off. 3. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore. 4. UART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 5. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 6. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode. 7. The I/Os with wakeup from Standby/Shutdown capability are PA0 and PA2. 8. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. |
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