công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

WM8580GEFV bảng dữ liệu(PDF) 43 Page - Wolfson Microelectronics plc

tên linh kiện WM8580GEFV
Giải thích chi tiết về linh kiện  Multichannel CODEC with S/PDIF Transceiver
PDF  92 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  WOLFSON [Wolfson Microelectronics plc]
Trang chủ  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8580GEFV bảng dữ liệu(HTML) 43 Page - Wolfson Microelectronics plc

Back Button WM8580GEFV Datasheet HTML 39Page - Wolfson Microelectronics plc WM8580GEFV Datasheet HTML 40Page - Wolfson Microelectronics plc WM8580GEFV Datasheet HTML 41Page - Wolfson Microelectronics plc WM8580GEFV Datasheet HTML 42Page - Wolfson Microelectronics plc WM8580GEFV Datasheet HTML 43Page - Wolfson Microelectronics plc WM8580GEFV Datasheet HTML 44Page - Wolfson Microelectronics plc WM8580GEFV Datasheet HTML 45Page - Wolfson Microelectronics plc WM8580GEFV Datasheet HTML 46Page - Wolfson Microelectronics plc WM8580GEFV Datasheet HTML 47Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 43 / 92 page
background image
Product Preview
WM8580
w
PP Rev 1.0 March 2006
43
SECONDARY AUDIO INTERFACES (SAIF RX & SAIF TX)
The Transmit and Receive sides of the Secondary Audio Interface share a common LRCLK and a
common BCLK. These can be supplied externally (slave mode) or they can be generated internally
by the WM8580 (master mode). The master mode LRCLK/BCLK are created by the Master Mode
Clock Gen module. The control of this module is described on page 21.
The clock supplied to this module can be ADCMCLK, PLLACLK, PLLBCLK, or MCLK and is selected
using the SAIFMS_CLKSEL register. If the digital routing has been configured such that the SAIF
Transmitter is sourcing the S/PDIF Receiver, then PLLACLK is automatically selected, and it is
recommended that the interface operate in master mode. However, if the SAIF Transmitter sources
something other than the S/PDIF Receiver, and the S/PDIF Receiver is powered up, the PLLACLK
and PLLBCLK are invalid for SAIF operation, so the choice is limited to ADCMCLK (default) or
MCLK.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R11
SAIF 1
0Bh
7:6
SAIFMS_
CLKSEL
11
SAIF Master Mode clock source
00 = ADCMCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
Table 37 SAIF Master Mode Clock Control
Figure 30 SAIF Clock Selection



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com