WM8580GEFV datasheet(35/92 Pages) WOLFSON

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WM8580

PP Rev 1.0 March 2006

ADC FEATURES

ADC HIGH-PASS FILTER DISABLE

The ADC digital filters incorporate a digital high-pass filter. By default, this is enabled but can be

disabled by setting the ADCHPD register bit to 1. This allows the input to the ADC to be DC coupled.

BIT

LABEL

DEFAULT

DESCRIPTION

R29

ADC CONTROL 1

1Dh

ADCHPD

ADC high-pass filter disable

0 = high-pass filter enabled

1 = high-pass filter disabled

Table 29 ADC Functions Register

ADC OVERSAMPLING RATE SELECT

The internal ADC signal processing operates at an oversampling rate of 128fs for all MCLK:LRCLK

ratios. The exception to this is for operation with a 128fs or 192fs master clock, where the internal

oversampling rate of the ADC is 64fs.

For ADC operation at 96kHz in 256fs or 384fs mode it is recommended that the user set the

ADCOSR bit. This changes the ADC signal processing oversampling rate from 128fs to 64fs.

Similarly, for ADC operation at 192kHz in 128fs or 192fs mode it is recommended that the user set

the ADCOSR bit to change the oversampling rate from 64fs to 32fs.

BIT

LABEL

DEFAULT

DESCRIPTION

R29

ADC CONTROL 1

1Dh

ADCOSR

ADC oversample rate select

0 = 128/64x oversampling

1 = 64/32x oversampling

Table 30 ADC Functions Register

ADC MUTE

As with the DAC, each ADC channel also has a mute control bit, which mutes the inputs to the ADC.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

AMUTEL

ADC Mute select

0 : Normal Operation

1: mute ADC left

AMUTER

ADC Mute select

0 : Normal Operation

1: mute ADC right

R29

ADC CONTROL 1

1Dh

AMUTEALL

ADC Mute select

0 : Normal Operation

1: mute both ADC channels

Table 31 ADC Mute Register

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