P87LPC779FDH datasheet(14/74 Pages) PHILIPS

14 / 74 page

Philips Semiconductors

P87LPC779

CMOS single-chip 8-bit microcontroller

Product data

Rev. 02 — 03 May 2004

14 of 74

9397 750 13213

8.4 A/D timing

The A/D may be clocked in one of two ways. The default is to use the CPU clock as

the A/D clock source. When used in this manner, the A/D completes a conversion in

31 machine cycles. The A/D may be operated up to the maximum CPU clock rate of

20 MHz, giving a conversion time of 9.3

µs. The formula for calculating A/D

conversion time when the CPU clock runs the A/D is: 186

µs / CPU clock rate

(in MHz). To obtain accurate A/D conversion results, the CPU clock must be at least

1 MHz.

The A/D may also be clocked by the on-chip RC oscillator, even if the RC oscillator is

not used as the CPU clock. This is accomplished by setting the RCCLK bit in

ADCON. This arrangement has several advantages. First, the A/D conversion time is

faster at lower CPU clock rates. Also, the CPU may be run at speeds below 1 MHz

without affecting A/D accuracy. Finally, the Power-down mode may be used to

completely shut down the CPU and its oscillator, along with other peripheral

functions, in order to obtain the best possible A/D accuracy.

ADCI

A/D conversion complete/interrupt ﬂag. This ﬂag is set when an

A/D conversion is completed. This bit will cause a hardware

interrupt if enabled and of sufﬁcient priority. Must be cleared by

software.

ADCS

A/D start. Setting this bit by software starts the conversion of the

selected A/D input. ADCS remains set while the A/D conversion is

in progress and is cleared automatically upon completion. While

ADCS or ADCI are one, new start commands are ignored. See

Table 6.

RCCLK

When RCCLK = 0, the CPU clock is used as the A/D clock. When

RCCLK = 1, the internal RC oscillator is used as the A/D clock.

This bit is writable while ADCS and ADCI are 0.

1, 0

AADR1, 0

Along with AADR0, selects the A/D channel to be converted.

These bits can only be written while ADCS and ADCI are 0. See

Table 7.

Table 6:

ADCON - ADCI, ADCS A/D status

ADCI, ADCS

A/D status

0 0

A/D not busy, a conversion can be started

0 1

A/D busy, the start of a new conversion is blocked.

1 0

An A/D conversion is complete. ADCI must be cleared prior to starting a

new conversion.

1 1

An A/D conversion is complete. ADCI must be cleared prior to starting a

new conversion. This state exists for one machine cycle as an A/D

conversion is completed.

Table 7:

ADCON - AADR1, AADR0 A/D input selection

AADR1, AADR0

A/D input selected

0 0

AD0 (P0.3)

0 1

AD1 (P0.4)

Table 5:

ADCON - A/D control register (address C0h) bit description…continued

Bit

Symbol

Description

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