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P87LPC779FDH bảng dữ liệu(PDF) 47 Page - NXP Semiconductors |
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P87LPC779FDH bảng dữ liệu(HTML) 47 Page - NXP Semiconductors |
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47 / 74 page ![]() Philips Semiconductors P87LPC779 CMOS single-chip 8-bit microcontroller Product data Rev. 02 — 03 May 2004 47 of 74 9397 750 13213 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 8.15.6 Baud rates The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = CPU clock/6. The baud rate in Mode 2 depends on the value of bit SMOD1 in Special Function Register PCON. If SMOD1 = 0 (which is the value on reset), the baud rate is 1 ⁄ 32 of the CPU clock frequency. If SMOD1 = 1, the baud rate is 1 ⁄ 16 of the CPU clock frequency. (4) Table 37: SCON - Serial port control register (address 98H) bit description Bit Symbol Description 7 FE Framing Error. This bit is set by the UART receiver when an invalid stop bit is detected. Must be cleared by software. The SMOD0 bit in the PCON register must be ‘1’ for this bit to be accessible. See SM0 bit below. SM0 With SM1, defines the serial port mode. The SMOD0 bit in the PCON register must be ‘0’ for this bit to be accessible. See FE bit above. 6 SM1 With SM0, defines the serial port mode (see Table 38 below). 5 SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then Rl will not be activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. In Mode 0, SM2 should be 0. 4 REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. 3 TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. 2 RB8 In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. 1 TI Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. 0 RI Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. Table 38: SM0, SM1 serial port mode SM0, SM1 UART mode Baud rate 0 0 0: shift register CPU clock/6 0 1 1: 8-bit UART variable (see text) 1 0 2: 9-bit UART CPU clock/32 or CPU clock/16 1 1 3: 9-bit UART variable (see text) Mode 2 baud rate 1 SMOD1 + 32 ------------------------------ CPU clock frequency × = |
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