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AT45DB021E

DS-AT45DB021E—8789J—03/2021

11.2 Ultra-Deep Power-Down

The Ultra-Deep Power-Down mode allows the device to consume far less power compared to the standby and

Deep Power-Down modes by shutting down additional internal circuitry. Since almost all active circuitry is shut

down in this mode to conserve power, the contents of the Buffer cannot be maintained. Therefore, any data stored

in the Buffer are lost once the device enters the Ultra-Deep Power-Down mode.

When the device is in the Ultra-Deep Power-Down mode, all commands including the Status Register Read and

Resume from Deep Power-Down commands are ignored. Since all commands are ignored, the mode can be used

as an extra protection mechanism against program and erase operations.

Entering the Ultra-Deep Power-Down mode is done by asserting the CS pin, clocking in the opcode 79h, and then

deasserting the CS pin. Any additional data clocked into the device after the opcode are ignored. When the CS pin

is deasserted, the device enters the Ultra-Deep Power-Down mode within the maximum time of tEUDPD.

The complete opcode must be clocked in before the CS pin is deasserted; otherwise, the device aborts the

operation and returns to the standby mode once the CS pin is deasserted. Also, the device defaults to the standby

mode after a power cycle.

The Ultra-Deep Power-Down command is ignored if an internally self-timed operation such as a program or erase

cycle is in progress. The Ultra-Deep Power-Down command must be reissued after the internally self-timed

operation has been completed in order for the device to enter the Ultra-Deep Power-Down mode.

Figure 11-3. Ultra-Deep Power-Down Timing

SCK

MSB

ICC

Opcode

High-impedance

Ultra-Deep Power-Down Mode Current

Active Current

Standby Mode Current

EUDPD

1111001

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