AT45DB021E datasheet(30/74 Pages) DIALOG

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AT45DB021E

DS-AT45DB021E—8789J—03/2021

in the Status Register indicates that the device is busy. If the device is powered-down during the program cycle,

then the contents of the 64-byte user programmable portion of the Security Register cannot be guaranteed.

If the full 64 bytes of data are not clocked in before the CS pin is deasserted, then the values of the byte locations

not clocked in cannot be guaranteed.

Example:

If only the first two bytes are clocked in instead of the complete 64 bytes, then the remaining 62 bytes of the

user programmable portion of the Security Register cannot be guaranteed. Furthermore, if more than 64

bytes of data is clocked into the device, the data wraps back around to the beginning of the register. For

example, if 65 bytes of data are clocked in, then the 65th byte is stored at byte location 0 of the Security

Warning:

The user programmable portion of the Security Register can only be programmed one time.

Therefore, it is

not possible, for example, to only program the first two bytes of the register and then program the remaining

62 bytes at a later time.

The Program Security Register command uses the internal buffer for processing. Therefore, the contents of

the Buffer are altered from their previous state when this command is issued.

Figure 9-4. Program Security Register Timing

9.2.2

Reading the Security Register

To read the Security Register, an opcode of 77h and three dummy bytes must be clocked into the device. After the

last dummy bit has been clocked in, the contents of the Security Register can be clocked out on the SO pin. After

the last byte of the Security Register has been read, additional pulses on the SCK pin result in undefined data

being output on the SO pin.

Deasserting the CS pin terminates the Read Security Register operation and put the SO pin into a high-impedance

state.

Figure 9-5. Read Security Register Timing

Data

9Bh

00h

Data

n + 1

Data

n + 63

Each transition represents eight bits

77h

Data

n + 1

Data

n + x

Each transition represents eight bits

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