PRT2011CVL4A datasheet(85/113 Pages) NXP

85 / 113 page

Boot mode configuration

i.MX RT1064 Crossover Processors for Industrial Products, Rev. 2, 08/2020

NXP Semiconductors

GPIO_EMC_34

semc.DATA[12]

ALT 0

—

GPIO_EMC_35

semc.DATA[13]

ALT 0

—

GPIO_EMC_36

semc.DATA[14]

ALT 0

—

GPIO_EMC_37

semc.DATA[15]

ALT 0

—

GPIO_EMC_09

semc.ADDR[0]

ALT 0

—

GPIO_EMC_10

semc.ADDR[1]

ALT 0

—

GPIO_EMC_11

semc.ADDR[2]

ALT 0

—

GPIO_EMC_12

semc.ADDR[3]

ALT 0

—

GPIO_EMC_13

semc.ADDR[4]

ALT 0

—

GPIO_EMC_14

semc.ADDR[5]

ALT 0

—

GPIO_EMC_15

semc.ADDR[6]

ALT 0

—

GPIO_EMC_16

semc.ADDR[7]

ALT 0

—

GPIO_EMC_19

semc.ADDR[11]

ALT 0

—

GPIO_EMC_20

semc.ADDR[12]

ALT 0

—

GPIO_EMC_21

semc.BA0

ALT 0

—

GPIO_EMC_22

semc.BA1

ALT 0

—

GPIO_EMC_41

semc.CSX[0]

ALT 0

—

Table 75. Boot through FlexSPI

PAD Name

IO Function

Mux Mode

Comments

GPIO_SD_B1_00

flexspi.B_DATA[3]

ALT 1

—

GPIO_SD_B1_01

flexspi.B_DATA[2]

ALT 1

—

GPIO_SD_B1_02

flexspi.B_DATA[1]

ALT 1

—

GPIO_SD_B1_03

flexspi.B_DATA[0]

ALT 1

—

GPIO_SD_B1_04

flexspi.B_SCLK

ALT 1

—

GPIO_SD_B0_05

flexspi.B_DQS

ALT 4

—

GPIO_SD_B0_04

flexspi.B_SS0_B

ALT 4

—

GPIO_SD_B0_01

flexspi.B_SS1_B

ALT 6

—

GPIO_SD_B1_05

flexspi.A_DQS

ALT 1

—

GPIO_SD_B1_06

flexspi.A_SS0_B

ALT 1

—

GPIO_SD_B0_00

flexspi.A_SS1_B

ALT 6

—

GPIO_SD_B1_07

flexspi.A_SCLK

ALT 1

—

GPIO_SD_B1_08

flexspi.A_DATA[0]

ALT 1

—

GPIO_SD_B1_09

flexspi.A_DATA[1]

ALT 1

—

Table 74. Boot trough NOR

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