PRT2011CVL4A datasheet(59/113 Pages) NXP

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Electrical Characteristics

i.MX RT1064 Crossover Processors for Industrial Products, Rev. 2, 08/2020

NXP Semiconductors

Figure 32. SAI timing—Slave mode

4.7.2

SPDIF timing parameters

The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When

encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.

Table 52 and Figure 33 and Figure 34 show SPDIF timing parameters for the Sony/Philips Digital

Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for

SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.

S17

SAI_RXD setup before SAI_BCLK

—

S18

SAI_RXD hold after SAI_BCLK

—

Table 52. SPDIF timing parameters

Characteristics

Symbol

Timing Parameter Range

Unit

Min

Max

SPDIF_IN Skew: asynchronous inputs, no specs apply

—

0.7

SPDIF_OUT output (Load = 50pf)

• Skew

• Transition rising

• Transition falling

—

1.5

24.2

31.3

SPDIF_OUT1 output (Load = 30pf)

• Skew

• Transition rising

• Transition falling

—

1.5

13.6

18.0

Modulating Rx clock (SPDIF_SR_CLK) period

srckp

40.0

—

Table 51. Slave mode SAI timing

Num

Characteristic

Min

Max

Unit

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