PRT2011CVL4A datasheet(49/113 Pages) NXP

tên linh kiện	PRT2011CVL4A

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Electrical Characteristics

i.MX RT1064 Crossover Processors for Industrial Products, Rev. 2, 08/2020

NXP Semiconductors

Figure 19. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0, 0X1

NOTE

Timing shown is based on the memory generating read data on the SCK

falling edge, and FlexSPI controller sampling read data on the falling edge.

4.5.2.1.2

SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3

There are two cases when the memory provides both read data and the read strobe in SDR mode:

•

A1—Memory generates both read data and read strobe on SCK rising edge (or falling

edge)

•

A2—Memory generates read data on SCK falling edge and generates read strobe on

SCK rising edgeSCK rising edge

Figure 20. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A1)

Table 39. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case A1)

Symbol

Parameter

Value

Unit

Min

Max

Frequency of operation

—

166

MHz

TSCKD

Time from SCK to data valid

—

TSCKDQS

Time from SCK to DQS

—

TSCKD - TSCKDQS

Time delta between TSCKD and TSCKDQS

-2

TIS

TIH

SCK

SIO[0:7]

TIS

TIH

Internal Sample Clock

TSCKDQS

SCK

SIO[0:7]

DQS

TSCKD

TSCKDQS

TSCKD

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