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ATMEGA640 bảng dữ liệu(PDF) 166 Page - Microchip Technology |
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ATMEGA640 bảng dữ liệu(HTML) 166 Page - Microchip Technology |
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166 / 436 page ![]() 166 ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 18.4 Register Description 18.4.1 GTCCR – General Timer/Counter Control Register • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is writ- ten to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting simultaneously. • Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters When this bit is one, Timer/Counter0, Timer/Counter1, Timer/Counter3, Timer/Counter4 and Timer/Counter5 pres- caler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter0, Timer/Counter1, Timer/Counter3, Timer/Counter4 and Timer/Counter5 share the same prescaler and a reset of this prescaler will affect all timers. Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM – – – – – PSRASY PSRSYNC GTCCR Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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