ATMEGA640 datasheet(164/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

18. Timer/Counter 0, 1, 3, 4, and 5 Prescaler

Timer/Counter 0, 1, 3, 4, and 5 share the same prescaler module, but the Timer/Counters can have different pres-

caler settings. The description below applies to all Timer/Counters. Tn is used as a general name, n = 0, 1, 3, 4, or

18.1 Internal Clock Source

The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fast-

est operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O).

Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a fre-

quency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024.

18.2 Prescaler Reset

The prescaler is free running, that is, operates independently of the Clock Select logic of the Timer/Counter, and it

is shared by the Timer/Counter Tn. Since the prescaler is not affected by the Timer/Counter’s clock select, the

state of the prescaler will have implications for situations where a prescaled clock is used. One example of presca-

ling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of

system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock

cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).

It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care

must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset

will affect the prescaler period for all Timer/Counters it is connected to.

18.3 External Clock Source

An external clock source applied to the Tn pin can be used as Timer/Counter clock (clkTn). The Tn pin is sampled

once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed

through the edge detector. Figure 18-1 shows a functional equivalent block diagram of the Tn synchronization and

edge detector logic. The registers are clocked at the positive edge of the internal system clock (clk

I/O). The latch is

transparent in the high period of the internal system clock.

The edge detector generates one clkTn pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it

detects.

Figure 18-1. Tn/T0 Pin Sampling

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has

been applied to the Tn pin to the counter is updated.

Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock

cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Tn_sync

(To Clock

Select Logic)

Edge Detector

Synchronization

clk

I/O

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