ATMEGA640 datasheet(204/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

22.3.4

Synchronous Clock Operation

When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input (Slave) or clock

output (Master). The dependency between the clock edges and data sampling or data change is the same. The

basic principle is that data input (on RxDn) is sampled at the opposite XCKn clock edge of the edge the data output

(TxDn) is changed.

Figure 22-3. Synchronous Mode XCKn Timing.

The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is used for data

change. As Figure 22-3 shows, when UCPOLn is zero the data will be changed at rising XCKn edge and sampled

at falling XCKn edge. If UCPOLn is set, the data will be changed at falling XCKn edge and sampled at rising XCKn

edge.

22.4 Frame Formats

A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and option-

ally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats:

•

1 start bit

•

5, 6, 7, 8, or 9 data bits

•

no, even or odd parity bit

•

1 or 2 stop bits

A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of

nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits,

before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the com-

munication line can be set to an idle (high) state. Figure 22-4 illustrates the possible combinations of the frame

formats. Bits inside brackets are optional.

Figure 22-4. Frame Formats

Start bit, always low.

(n)

Data bits (0 to 8).

Parity bit. Can be odd or even.

Stop bit, always high.

IDLE

No transfers on the communication line (RxDn or TxDn). An IDLE line must be high.

RxD / TxD

XCK

RxD / TxD

XCK

UCPOL = 0

UCPOL = 1

Sample

[5]

[6]

[7]

[8]

[P]

Sp1 [Sp2]

(St / IDLE)

(IDLE)

FRAME

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