VSC8221 datasheet(126/138 Pages) MICROSEMI

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VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

126 of 132

132

31 DESIGN GUIDELINES

Although copper-based Ethernet physical layer devices (PHY) have been developed from an established iEEE standard, some

PHYs available in the marketplace are either non-compliant with the standard or implement non-standard features that cause

interoperability issues with the SimpliPHYTM series of gigabit Ethernet PHYs.

31.1 Required PHY Register Write Sequence

issue: At initialization, a number of internal registers must be changed from their default values.

Description: A series of register writes must be performed after device power-up or reset. These writes can be done using the

EEPROM connected to the EEPROM interface or by the Switch/Station Manager.

Workaround: The required register writes are as follows:

• 2A30h to PHY Register 31

• 0212h to PHY Register 8

• 52B5h to PHY Register 31

• 000Fh to PHY Register 2

• 472Ah to PHY Register 1

• 8FA4h to PHY Register 0

• 2A30h to PHY Register 31

• 0012h to PHY Register 8

• 0000h to PHY Register 31

31.2 interoperability with intel 82547Ei Gigabit Ethernet MAC+PHY iC

issue: Due to a non-standard startup-sequence in the intel 82547Ei MAC+PHY iC, the VSC8221 might take multiple attempts to

establish link.

Workaround: The following PHY register write can be performed to avoid this issue:

• 0049h to Mii Register 18

31.3 SerDes Jitter

issue: Under worst case conditions, total jitter performance may exceed the iEEE specifications for 1000BASE-X, as noted in

the table below.

impact: in typical applications with robust PCB design practices, however, actual performance is typically better than the figures

noted below.

Workaround: None.

Symbol

Min

Typ

Max

Unit

Parameter Description and Conditions

J(TOTAL, TX)

290

Worst case total transmit jitter in media converter

applications.

J(TOTAL, RX)

400

Worst case total receive jitter tolerance in media

converter applications.

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