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VSC8221 bảng dữ liệu(PDF) 9 Page - Microsemi Corporation |
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VSC8221 bảng dữ liệu(HTML) 9 Page - Microsemi Corporation |
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9 / 138 page ![]() VSC8221 Data Sheet VMDS-10106 Revision 4.1 December 2006 9 of 10 10 23.3.11 Register 26E (1Ah) - Reserved ..........................................................................................................104 23.3.12 Register 27E (1Bh) - Reserved ..........................................................................................................104 23.3.13 Register 28E (1Ch) - Reserved ..........................................................................................................104 23.3.14 Register 29E (1Dh) - 1000BASE-T Ethernet Packet Generator (EPG) Register #1 ..................... 105 23.3.15 Register 30E (1Eh) - 1000BASE-T Ethernet Packet Generator Register #2 .................................106 24 Electrical Specifications ............................................................................................................................................ 107 24.1 Absolute Maximum Ratings .............................................................................................................. 107 24.2 Recommended Operating Conditions .............................................................................................. 107 24.3 Thermal Application Data ................................................................................................................. 108 24.4 Package Thermal Specifications - 100 TFBGA ................................................................................ 109 24.5 Current and Power Consumption Estimates .................................................................................... 109 25 DC Specifications ....................................................................................................................................................... 114 25.1 Digital Pins (VDDiO = 3.3 V) ............................................................................................................. 114 25.2 Digital Pins (VDDiO = 2.5 V) ............................................................................................................. 114 25.3 LED Output Pins (LED[2:0]) ............................................................................................................. 115 26 Clocking Specifications ............................................................................................................................................. 116 26.1 Reference Clock Option ................................................................................................................... 116 26.2 Crystal Option ................................................................................................................................... 116 27 SerDes Specifications ................................................................................................................................................ 117 28 System Timing Specifications .................................................................................................................................. 118 28.1 JTAG Timing ..................................................................................................................................... 118 28.2 SMi Timing ........................................................................................................................................ 119 28.3 MDiNT Timing ................................................................................................................................... 120 28.4 Serial LED_CLK and LED_DATA Timing ......................................................................................... 120 28.5 REFCLK Timing ................................................................................................................................ 121 28.6 CLKOUT and CLKOUTMiCRO Timing ............................................................................................. 122 28.7 Reset Timing .................................................................................................................................... 123 29 Packaging Specifications .......................................................................................................................................... 124 29.1 100-Ball 9 × 9mm TFBGA Mechanical Specification ........................................................................ 124 29.2 Package Moisture Sensitivity ............................................................................................................ 124 30 Ordering information .................................................................................................................................................. 125 30.1 Devices ............................................................................................................................................. 125 31 Design Guidelines ....................................................................................................................................................... 126 31.1 Required PHY Register Write Sequence .......................................................................................... 126 31.2 interoperability with intel 82547Ei Gigabit Ethernet MAC+PHY iC ................................................... 126 31.3 SerDes Jitter ..................................................................................................................................... 126 31.4 SGMii 100BASE-TX Corruption of Packets with Odd Preambles .................................................... 127 |
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