VSC8221 datasheet(79/138 Pages) MICROSEMI

79 / 138 page

VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

79 of 106

106

10.14 – MASTER/SLAVE Configuration Resolution1

By default, the MASTER/SLAVE configuration is determined as part of the auto-negotiation process. However, the MASTER/

SLAVE status can optionally be manually forced via bits in Mii Register 9. Bit 10.14 indicates the final MASTER/SLAVE

configuration status for the local PHY. This bit can change state only as a result of the reset or subsequent restart of the auto-

negotiation process. This bit is only valid when the Auto-Negotiation Complete bit (1.5) is set.

10.13 – Local Receiver Status1

Bit 10.13 indicates the state of the loc_rcvr_status flag within the PMA receive function within the local PHY.

10.12 – Remote Receiver Status1

Bit 10.12 indicates the state of the rem_rcvr_status flag within the PMA receive function within the local PHY.

10.11 – LP 1000BASE-T FDX Capability1

Bit 10.11 is set to “1” if the Link Partner PHY advertises 1000BASE-T FDX capability. Otherwise, this bit is set to “0”. The state

of this bit is valid when the Auto-Negotiation Complete bit (1.5) is set.

10.10 – LP 1000BASE-T HDX Capability1

Bit 10.10 is set to “1” if the Link Partner PHY advertises 1000BASE-T HDX capability. Otherwise, this bit is set to “0”. The state

of this bit is valid when the Auto-Negotiation Complete bit (1.5) is set.

10.9:8 – Reserved

10.7:0 – idle Error Count1

Bits 10.7:0 indicate the idle Error count, where 10.7 is the most significant bit. These bits contain a cumulative count of the

errors detected when the receiver is receiving idles and PMA_TXMODE.indicate is equal to SEND_N (indicating that both the

local and remote receiver status have been detected to be OK). The counter is incremented every symbol period that

rx_error_status in the PMA receive function is equal to ERROR. Bits 10.7:0 are reset to all “0”s when the error count is read by

the management function, or upon execution of the PCS reset function, and they are saturated to all “1”s in case of overflow.

23.2.12 Register 11 (0Bh) – Reserved Register

11.15:0 – Reserved

1This bit is valid only when the Page Received bit (6.1) is set to a “1” and if Mii Register bit 9.9 or 9.8 is set.

Bit

Name

Access

States

Reset Value

Sticky

15:0

Reserved

00000000 00000000

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