VSC8221 datasheet(82/138 Pages) MICROSEMI

82 / 138 page

VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

82 of 106

106

18.15 – Reserved

18.14 – Bypass 4B5B Encoder/Decoder 1

When bit 18.14 is set to “1”, the 5B codes (TXER and TXD[3:0]) will be passed from the Mii interface directly to the scrambler,

bypassing the 4B5B encoder. Note that in this mode, J/K and T/R code insertion will not be performed. The receiver will pass

descrambled/aligned 5B codes directly to the Mii interface (RXER and RXD[3:0]), bypassing the 4B5B decoder. Carrier sense

(CRS) is still asserted when a valid frame is detected.

18.13 – Bypass Scrambler2

When bit 18.13 is set to “1”, the scrambler is disabled.

18.12 – Bypass Descrambler2

When bit 18.12 is set to “1”, the descrambler is disabled.

18.11:9 – Reserved

18.8 – Transmitter Test Clock Enable

When a “1” is written to bit 18.8, the CLKOUTMiCRO output pin becomes a test pin for the transmit clock “TXCLK”. This

capability is intended to enable measurement of transmitter timing jitter, as specified in iEEE Standard 802.3-2002, section

40.6.1.2.5. When in iEEE-specified transmitter test modes 2 or 3 (see iEEE 802.3-2002, section 40.6.1.1.2 and Mii Register bits

9.15:13), the peak-to-peak jitter of the zero-crossings of the differential signal output at the MDi, relative to the corresponding

edge of TXCLK, is measured. The corresponding edge of TXCLK is the edge of the transmit test clock, in polarity and time, that

generates the zero-crossing transition being measured.

While transmitter test mode clock TXCLK is intended only for characterization test purposes, CLKOUTMiCRO is intended to

serve as a general purpose system or MAC reference clock.

18.7:6 – Reserved

7:6

Reserved

Disable Automatic Pair Swap Cor-

rection

R/W

1=Disable

0=Enable

Disable Polarity inversion

R/W

1=Disable

0=Enable

Parallel-Detect Control

R/W

1 = Do not ignore advertised ability

0 = ignore advertised ability

Reserved

Disable Automatic 1000BASE-T

Next-Page Exchange

R/W

1 = Disable automatic 1000BASE-T Next-Page

exchanges

0 = Enable automatic 1000BASE-T Next-Page

exchanges

CLKOUT Output Enable

R/W

1 = Enable output clock pins CLKOUT

0 = Disable output clock pins CLKOUT

1This bit applies only in 100BASE-TX mode.

2This bit applies only in 100BASE-TX and 1000BASE-T modes.

Bit

Name

Access

States

Reset

Value

Sticky

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