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STM32G041C6M3TR bảng dữ liệu(PDF) 91 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  Arm® Cortex®-M0 32-bit MCU, up to 64 KB Flash, 8 KB RAM, 2x USART, timers, ADC, comm. I/Fs, AES, RNG, 1.7-3.6V
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STM32G041C6M3TR bảng dữ liệu(HTML) 91 Page - STMicroelectronics

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DS12993 Rev 2
91/118
STM32G041x6/x8
Electrical characteristics
93
Figure 30. I2S slave timing diagram (Philips protocol)
1. Measurement points are done at CMOS levels: 0.3 VDDIO1 and 0.7 VDDIO1.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
tv(WS)
WS valid time
Master mode
-
6
ns
th(WS)
WS hold time
Master mode
3
-
tsu(WS)
WS setup time
Slave mode
3
-
th(WS)
WS hold time
Slave mode
2
-
tsu(SD_MR)
Data input setup time
Master receiver
4
-
tsu(SD_SR)
Slave receiver
5
-
th(SD_MR)
Data input hold time
Master receiver
4.5
-
th(SD_SR)
Slave receiver
2
-
tv(SD_ST)
Data output valid time -
slave transmitter
after enable edge; 2.7 < VDD < 3.6V
-
10
after enable edge; 1.65 < VDD < 3.6V
15
tv(SD_MT)
Data output valid time -
master transmitter
after enable edge
-
5.5
th(SD_ST)
Data output hold time -
slave transmitter
after enable edge
7
-
th(SD_MT)
Data output hold time -
master transmitter
after enable edge
1
-
1. Based on characterization results, not tested in production.
Table 69. I2S characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
MSv39721V1
CPOL = 0
CPOL = 1
tc(CK)
WS input
SDtransmit
SDreceive
tw(CKH)
tw(CKL)
tsu(WS)
tv(SD_ST)
th(SD_ST)
th(WS)
tsu(SD_SR)
th(SD_SR)
MSB receive
Bitn receive
LSB receive
MSB transmit
Bitn transmit
LSB receive(2)
LSB transmit(2)



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