STM32G031F6 datasheet(68/117 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32G031x4/x6/x8

68/117

DS12992 Rev 2

5.3.12

Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the ANSI/JEDEC standard.

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up

performance:

•

A supply overvoltage is applied to each power supply pin.

•

A current is injected to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 47. EMI characteristics

Symbol

Parameter

Conditions

Monitored

frequency band

Max vs.

[fHSE/fHCLK]

Unit

8 MHz / 64 MHz

SEMI

Peak level

VDD = 3.6 V, TA = 25 °C,

LQFP64 package

compliant with IEC 61967-2

0.1 MHz to 30 MHz

-4

dBµV

30 MHz to 130 MHz

130 MHz to 1 GHz

1 GHz to 2 GHz

EMI level

2.5

Table 48. ESD absolute maximum ratings

Symbol

Ratings

Conditions

Class

Maximum

value(1)

Unit

VESD(HBM)

Electrostatic discharge voltage

(human body model)

TA = +25 °C, conforming to

ANSI/ESDA/JEDEC JS-001

1000

VESD(CDM)

Electrostatic discharge voltage

(charge device model)

TA = +25 °C, conforming to

ANSI/ESDA/JEDEC JS-002

C2a

500

1. Based on characterization results, not tested in production.

Table 49. Electrical sensitivity

Symbol

Parameter

Conditions

Class

Static latch-up class

TA = +125 °C conforming to JESD78

II Level A

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