ADSP-SC571KSWZ-4 datasheet(21/142 Pages) AD

21 / 142 page

Rev. B

Page 21 of 142

June 2018

ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573

The two capacitors and the series resistor, shown in Figure 6,

fine tune phase and amplitude of the sine frequency. The capac-

itor and resistor values shown in Figure 6 are typical values

only. The capacitor values are dependent upon the load capaci-

tance recommendations of the crystal manufacturer and the

physical layout of the printed circuit board (PCB). The resistor

value depends on the drive level specified by the crystal manu-

facturer. The user must verify the customized values based on

careful investigations on multiple devices over the required

temperature range.

A third overtone crystal can be used for frequencies above

25 MHz. The circuit is then modified to ensure crystal operation

only at the third overtone by adding a tuned inductor circuit,

shown in Figure 6. A design procedure for third overtone opera-

tion is discussed in detail in “Using Third Overtone Crystals

with the ADSP-218x DSP” (EE-168). The same recommenda-

tions can be used for the USB crystal oscillator.

Clock Distribution Unit (CDU)

The two CGUs each provide outputs which feed a clock distri-

bution unit (CDU). The clock outputs CLKO0–CLKO9 are

connected to various targets. For more information, refer to the

ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware

Reference.

Power-Up

SYS_XTALx oscillations (SYS_CLKINx) start when power is

applied to the VDD_EXT pins. The rising edge of SYS_HWRST

starts on-chip PLL locking (PLL lock counter). The deassertion

must apply only if all voltage supplies and SYS_CLKINx oscilla-

tions are valid (refer to the Power-Up Reset Timing section).

Clock Out/External Clock

The SYS_CLKOUT output pin has programmable options to

output divided-down versions of the on-chip clocks. By default,

the SYS_CLKOUT pin drives a buffered version of the

SYS_ CLKIN0 input. Refer to the ADSP-SC57x/ADSP-2157x

SHARC+ Processor Hardware Reference to change the default

mapping of clocks.

Booting

The processors have several mechanisms for automatically load-

ing internal and external memory after a reset. The boot mode is

defined by the SYS_BMODE[n] input pins. There are two cate-

gories of boot modes. In master boot mode, the processors

actively load data from serial memories. In slave boot modes,

the processors receive data from external host devices.

The boot modes are shown in Table 9. These modes are imple-

mented by the SYS_BMODE[n] bits of the reset configuration

initiated resets.

In the ADSP-SC57x processors, the ARM Cortex-A5 (Core 0)

controls the boot process, including loading all internal and

external memory. Likewise, in the ADSP-2157x processors, the

SHARC+ (Core 1) controls the boot function. The option for

secure boot is available on all models.

Thermal Monitoring Unit (TMU)

The thermal monitoring unit (TMU) provides on-chip tem-

perature measurement for applications that require substantial

power consumption. The TMU is integrated into the processor

die and digital infrastructure using an MMR-based system

access to measure the die temperature variations in real-time.

TMU features include the following:

• On-chip temperature sensing

• Programmable over temperature and under temperature

limits

• Programmable conversion rate

• Programmable clock source selection to run the sensor off

an independent local clock

• Averaging feature available

Power Supplies

The processors have separate power supply connections for

• Internal (VDD_INT)

• External (VDD_EXT)

• USB (VDD_USB)

• HADC/TMU (VDD_HADC)

• DMC (VDD_DMC)

All power supplies must meet the specifications provided in

Operating Conditions section. All external supply pins must be

connected to the same power supply.

Power Management

As shown in Table 10, the processors support four different

power domains, which maximizes flexibility while maintaining

compliance with industry standards and conventions. There are

no sequencing requirements for the various power domains, but

all domains must be powered according to the appropriate spec-

ifications (see the Specifications section for processor operating

conditions). If the feature or the peripheral is not used, refer to

Table 25.

Table 9. Boot Modes

SYS_BMODE[n] Setting1, 2 Boot Mode

000

No boot

001

SPI2 master

010

SPI2 slave

011

UART0 slave

100

Reserved

101

Reserved

110

Link0 slave

1 SYS_BMODE2 pin is applicable only for the BGA package.

2 Link0 slave boot is supported only on the BGA package.

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