ADSP-SC571KSWZ-4 datasheet(70/142 Pages) AD

70 / 142 page

Rev. B

Page 70 of 142

June 2018

ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573

DDR2 SDRAM Write Cycle Timing

Table 45 and Figure 12 show DDR2 SDRAM write cycle timing, related to the DMC.

Table 45. DDR2 SDRAM Write Cycle Timing, VDD_DMC Nominal 1.8 V

400 MHz1

1 To ensure proper operation of the DDR2, all the DDR2 requirements must be strictly followed. See “Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx

Processors” (EE-387).

Parameter

Min

Max

Unit

Switching Characteristics

tDQSS

DMC0_DQS Latching Rising Transitions to Associated Clock Edges2

2 Write command to first DMC0_DQS delay = WL × tCK + tDQSS.

–0.15

+0.15

tCK

tDS

Last Data Valid to DMC0_DQS Delay

0.1

tDH

DMC0_DQS to First Data Invalid Delay

0.15

tDSS

DMC0_DQS Falling Edge to Clock Setup Time

0.2

tCK

tDSH

DMC0_DQS Falling Edge Hold Time From DMC0_CK

0.2

tCK

tDQSH

DMC0_DQS Input High Pulse Width

0.35

tCK

tDQSL

DMC0_DQS Input Low Pulse Width

0.35

tCK

tWPRE

Write Preamble

0.35

tCK

tWPST

Write Postamble

0.4

tCK

tIPW

Address and Control Output Pulse Width

0.6

tCK

tDIPW

DMC0_DQ and DMC0_DM Output Pulse Width

0.35

tCK

Figure 12. DDR2 SDRAM Controller Output AC Timing

tDS

tDH

tDQSS

tDSH

tDSS

tWPRE

tDQSL

tDQSH

tWPST

DMC0_CK

tIPW

tDIPW

DMC0_LDQS/DMC0_UDQS

DMC0_CK

DMC0_Ax

DMC0 CONTROL

DMC0_DQSn

DMC0_LDM

DMC0_DQx

DMC0_UDM

NOTE: CONTROL =

DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.

ADDRESS = DMC0_A00-13 AND DMC0_BA0-1.

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