ADSP-SC571KSWZ-4 datasheet(92/142 Pages) AD

92 / 142 page

Rev. B

Page 92 of 142

June 2018

ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573

Asynchronous Sample Rate Converter (ASRC)—Serial Output Port

For the serial output port, the frame sync is an input and it must meet setup and hold times with regard to SCLK on the output port. The

serial data output has a hold time and delay specification with regard to serial clock. The serial clock rising edge is the sampling edge, and

the falling edge is the drive edge.

Figure 35. ASRC Serial Output Port Timing

Table 62. ASRC, Serial Output Port

Parameter

Min

Max

Unit

Timing Requirements

tSRCSFS

1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The input of

the PCG can be either CLKIN, SCLK0, or any of the DAI pins.

Frame Sync Setup Before Serial Clock Rising Edge

tSRCHFS

Frame Sync Hold After Serial Clock Rising Edge

5.5

tSRCCLKW

Clock Width

tSCLK0 – 1

tSRCCLK

Clock Period

2 × tSCLK0

Switching Characteristics

tSRCTDD

Transmit Data Delay After Serial Clock Falling Edge

tSRCTDH

Transmit Data Hold After Serial Clock Falling Edge

DAI0_PIN20–1

(SCLK)

SAMPLE EDGE

DAI0_PIN20–1

(FS)

DAI0_PIN20–1

(SDATA)

tSRCCLK

tSRCCLKW

tSRCSFS

tSRCHFS

tSRCTDD

tSRCTDH

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