ADSP-SC571KSWZ-4 datasheet(13/142 Pages) AD

13 / 142 page

Rev. B

Page 13 of 142

June 2018

ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573

periodic communication message objects. Dedicated hardware

circuitry compares the signature with precalculated values and

triggers appropriate fault events.

For example, every 100 ms the system software initiates the sig-

nature calculation of the entire memory contents and compares

these contents with expected, precalculated values. If a mis-

match occurs, a fault condition is generated through the

processor core or the trigger routing unit.

The CRC is a hardware module based on a CRC32 engine that

computes the CRC value of the 32-bit data-words presented to

it. The source channel of the memory to memory DMA (in

memory scan mode) provides data. The data can be optionally

forwarded to the destination channel (memory transfer mode).

The main features of the CRC peripheral are as follows:

• Memory scan mode

• Memory transfer mode

• Data verify mode

• Data fill mode

• User-programmable CRC32 polynomial

• Bit and byte mirroring option (endianness)

• Fault and error interrupt mechanisms

• 1D and 2D fill block to initialize an array with constants

• 32-bit CRC signature of a block of a memory or an MMR

block

Event Handling

The processors provide event handling that supports both nest-

ing and prioritization. Nesting allows multiple event service

routines to be active simultaneously. Prioritization ensures that

servicing a higher priority event takes precedence over servicing

a lower priority event.

The processors provide support for four different types of

events:

• An emulation event causes the processors to enter emula-

tion mode, allowing command and control of the

processors through the JTAG interface.

• A reset event resets the processors.

• An exceptions event occurs synchronously to program flow

(in other words, the exception is taken before the instruc-

tion is allowed to complete). Conditions triggered on the

one side by the SHARC+ core, such as data alignment

(SIMD or long word) or compute violations (fixed or float-

ing point), and illegal instructions cause core exceptions.

Conditions triggered on the other side by the SEC, such as

error correcting codes (ECC), parity, watchdog, or system

clock, cause system exceptions.

• An interrupts event occurs asynchronously to program

flow. They are caused by input signals, timers, and other

peripherals, as well as by an explicit software instruction.

System Event Controller (SEC)

Both SHARC+ cores feature a system event controller. The SEC

features include the following:

• Comprehensive system event source management, includ-

ing interrupt enable, fault enable, priority, core mapping,

and source grouping

• A distributed programming model where each system

event source control and all status fields are independent of

each other

• Determinism where all system events have the same propa-

gation delay and provide unique identification of a specific

system event source

• A slave control port that provides access to all SEC registers

for configuration, status, and interrupt and fault services

• Global locking that supports a register level protection

model to prevent writes to locked registers

• Fault management including fault action configuration,

time out, external indication, and system reset

Trigger Routing Unit (TRU)

The trigger routing unit (TRU) provides system level sequence

control without core intervention. The TRU maps trigger

masters (generators of triggers) to trigger slaves (receivers of

triggers). Slave endpoints can be configured to respond to trig-

gers in various ways. Common applications enabled by the TRU

include,

• Automatically triggering the start of a DMA sequence after

a sequence from another DMA channel completes

• Software triggering

• Synchronization of concurrent activities

SECURITY FEATURES

The following sections describe the security features of the

ADSP-SC57x/ADSP-2157x processors.

ARM TrustZone

The ADSP-SC57x processors provide TrustZone technology

that is integrated into the ARM Cortex-A5 processors. The

TrustZone technology enables a secure state that is extended

throughout the system fabric.

Cryptographic Hardware Accelerators

The ADSP-SC57x/ADSP-2157x processors support standards-

based hardware accelerated encryption, decryption, authentica-

tion, and true random number generation.

Support for the hardware accelerated cryptographic ciphers

includes the following:

• AES in ECB, CBC, ICM, and CTR modes with 128-bit,

192-bit, and 256-bit keys

• DES in ECB and CBC mode with 56-bit key

• 3DES in ECB and CBC mode with 3x 56-bit key

• ARC4 in stateful, stateless mode, up to 128-bit key

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