FS32K112BHTXMLLTR datasheet(95/100 Pages) NXP

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Table 57. Revision History

Rev. No.

Date

Substantial Changes

• Added footnote 'For S32K11x – FIRC/SOSC/FIRC/LPO; For S32K14x

– FIRC/SOSC/FIRC/LPO/SPLL' to 'VLPS Mode: All clock sources

disabled'

• Updated numbers for:

• VLPR → VLPS

• VLPS → VLPR

• 'RUN → Compute operation'

• RUN → VLPS

• RUN → VLPR

• In Power consumption :

• Updated specs for S32K142, S32K144, and S32K148

• Updated footnote 'Typical current numbers are indicative ...'

• Updated footnote 'The S32K148 data ...'

• Removed footnote 'Above S32K148 data is preliminary targets only'

• Added new table 'Power consumption at 3.3 V'

• In General AC specifications :

• Updated max value and footnote of WFRST

• Updated symbol for not filtered pulse to 'WNFRST', updated min value,

removed max. value, and added footnote

• Fixed naming conventions to align with DS in DC electrical specifications at

3.3 V Range and DC electrical specifications at 5.0 V Range

• Updated specs for AC electrical specifications at 3.3 V range and AC

electrical specifications at 5 V range

• In Device clock specifications :

• Updated fBUS to 48 for 11x

• Added footnote to fBUS for 14x

• In External System Oscillator frequency specifications :

• Added specs for S32K11x

• Updated 'tdc_extal' for S32K14x

• Added footnote 'Frequecies below ... ' to 'fec_extal' and 'tdc_extal'

• Splitted Flash timing specifications — commands for S32K14x and S32K11x

• Updated Flash timing specifications — commands for S32K14x

• In Reliability specifications :

• Added footnote 'Data retention period ... ' for 'tnvmretp1k' and

'tnvmretee'

• Minor update in footnote for 'nnvmwree16' 'nnvmwree256'

• In QuadSPI AC specifications :

• Updated 'MCR[SCLKCFG[5]]' value to 0

• Updated 'Data Input Setup Time' HSRUN Internal DQS PAD Loopback

value to 1.6

• Updated 'Data Input Setup Time' DDR External DQS min. value to 2

• Updated 'Data Input Hold Time' DDR External DQS min. value to 20

• Upadted figure 'QuadSPI output timing (SDR mode) diagram' and

'QuadSPI input timing (HyperRAM mode) diagram'

• In 12-bit ADC electrical characteristics :

• Added note 'On reduced pin packages where ... '

• Removed max. value of 'IDDA_ADC'

• Added note 'Due to triple ... '

• In 12-bit ADC operating conditions, removed parameter '

ΔVDDA'

• In CMP with 8-bit DAC electrical specifications :

• Updated Typ. and Max. values of 'IDDLS'

• Upadted Typ. value of 'tDHSB'

• Updated Typ. value of 'VHYST1' , 'VHYST2', and 'VHYST3'

• In LPSPI electrical specifications :

• Updated 'fperiph' and 'fop', and 'tSPSCK'

Table continues on the next page...

Revision History

S32K1xx Data Sheet, Rev. 12, 02/2020

NXP Semiconductors

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