W5100S datasheet(2/110 Pages) WIZNET

2 / 110 page

2 / 110

W5100S Datasheet Version1.2.5

W5100S

W5100S is an embedded Ethernet controller designed as a full hardwired TCP / IP with WIZnet

technology. W5100S provides internet connectivity to your embedded system by using SPI

(Serial Peripheral Interface) or Parallel System BUS.

SPI and Parallel System BUS provide easy connection via external MCU to W5100S.

The clock speed of W5100S SPI supports upto 70MHz and the Parallel System Bus supports

higher speed network communication than SPI.

Since W5100S integrates the Hardwired TCP/IP stack with 10/100 Ethernet MAC and PHY, it is

truly a one-chip solution for the stable internet connectivity.

WIZnet’s hardwired TCP/IP stack supports TCP, UDP, IPv4, ICMP, ARP, IGMP, and PPPoE - and

it has been proven through various applications over the last decade. W5100S provides four

independent SOCKETs to be used simultaneously and 16KB internal memory for data

communication. Users can develop an Ethernet application easily by using the simple W5100S

SOCKET program instead of handling a complex Ethernet controller. W5100S also provides

WOL (Wake on LAN) and a Power Down Mode in order to reduce power consumption.

W5100S is a low-cost chip that exceeds its predecessor, W5100.

Existing firmware using W5100 can be used on W5100S without modification.

W5100S has two types of packages, 48 Pin LQFP & QFN Lead-Free Package.

W5100S bảng dữ liệu(PDF) 2 Page - WIZnet Co., Ltd