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W5100S bảng dữ liệu(PDF) 87 Page - WIZnet Co., Ltd

tên linh kiện W5100S
Giải thích chi tiết về linh kiện  embedded Ethernet controller
PDF  110 Pages
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nhà sản xuất  WIZNET [WIZnet Co., Ltd]
Trang chủ  https://www.wiznet.io/ko/Product/
Logo WIZNET - WIZnet Co., Ltd

W5100S bảng dữ liệu(HTML) 87 Page - WIZnet Co., Ltd

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W5100S Datasheet Version1.2.5
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4.9
Others Function
4.9.1 System Clock(SYS_CLK) Switching
SYS_CLK is set 25MHz or 100MHz. It is switched by MR2 [CLKSEL], PHYCR1 [RST] or PHYCR1
[PWDN]. At switching Clock speed, Host must wait until stabilized SYS_CLK. (Ref 7.4.1 Reset
Timing)
MR2[CLKSEL]
PHYCR1[RST]
PHYCR1[PWDN]
SYS_CLK(MHz)
0
1
X
25
0
0
0
100 (Default)
0
1
1
25
1
X
X
25
4.9.2 Ethernet PHY Operation Mode Configuration
PHY Operation Mode (Speed, Duplex) set by PHYCR0 is applied after Ethernet PHY H/W Reset.
Set PHY Operation Mode is checked through PHYSR [5:3] and the state of Link is described on
PHYSR [2:0] after Ethernet PHY Link Up.
Before PHYCR0 is set, PHYLCKR must be unlocked.
Ex) How to set PHY Operation Mode
PHY_10FDX :
{
/* PHYCR0 & PHYCR1 Unlock */
PHYLCKR = 0x53;
/* set PHYCR0 10Mbps/Full-Duplex */
PHYCR0[DPX] = ‘0’;
// 0 – FDX, 1 - HDX;
PHYCR0[SPD] = ‘1’ ;
// 0 - 100Mbps, 1 – 10Mbps;
PHYCR0[AUTO] = ‘1’;
// 0 – Auto-negotiation, 1 – Manual;
/* PHY Reset Process */
PHYCR1[RST] = ‘1’;
Wait TPRST;
// refer to 7.4.1 Reset Timing
/*wait until PHY Link is up*/
while(PHYSR[LINK] != ‘0’);
/* read PHYSR */
If( (PHYSR[DPX] == ‘0’ ) & ( PHYSR[SPD] == ‘1’) & (PHYSR[AUTO] == ‘1’) ) SUCCESS;
else FAIL;



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