W5100S datasheet(109/110 Pages) WIZNET

109 / 110 page

W5100S Datasheet Version1.2.5

109 / 110

Document Revision History

Version

Date

Descriptions

Ver. 1.0.0

1APR2018

Initial Release

Ver. 1.0.1

2ARP2019

Edit typo & incorrect link

Ver. 1.1.0

5SEP2018

1. corrected reset timing in RSTn pin(500ns -> 560ns) (1.1 PIN

Description)

2. corrected INTPTMR register type (RW -> R=W) (3.1.6 INTPTMR

(Interrupt Pending Time Register))

3. modified PHYCR0 Bits symbol (AUTO/SPD/DPX->MODE[3:0])

(3.1.30 PHYCR0

(PHY Control Register 0))

4. added register, PHYSR1 (3.1.24 PHYSR1

(PHY Status Register

1))

5. modified the complete condition,PHYSR1[ACT]=‘1’, of reset by

PHYCR1[RST] (3.1.31 PHYCR1

(PHY Control Register 1))

6. corrected NETLCKR value, Lock(0x3A -> 0xC5), Unlock(0xC5 ->

0x3A) (3.1.42 NETLCKR

(Network Lock Register))

7. modified UDP received Data Size (Figure 9)

8. modified IPRAW received Data Size (Figure 11)

Ver. 1.2.0

13NOV2018

1. modified BUS access timing ( 7.4.2 BUS ACCESS TIMING )

Added TWRn, TRDn

Ver. 1.2.1

14NOV2018

1. modified BUS access timing (7.4.2 BUS ACCESS TIMING)

Modified Burst Mode

Ver. 1.2.2

23NOV2018

1. Modified Sn_MSS reset value (3.2.9 Sn_MSS (SOCKET n Maximum

Segment Size Register))

2. Modified Load capacitance value(12p -> 8p) (6.1 Quartz Crystal

requirements.)

Ver. 1.2.3

7JAN2019

1. Modified DC Characteristics (in 7.3 DC Characteristics)

Ver. 1.2.4

7MAR2019

1. Modified

Trans-conductance(gm)(8.43 -> 16) (6.1 Quartz

Crystal requirements.

2. Modified pin name of SPI/BUS Timing figure (in 7.4.2 BUS ACCESS

TIMING , 7.4.3 SPI ACCESS TIMING)

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