PIC16F15213 datasheet(48/420 Pages) MICROCHIP

48 / 420 page

Figure 9-7. Memory Map - Bank 62

1F47h

INLVLB

(1)

1F48h

IOCBP

(1)

1F49h

IOCBN

(1)

1F4Ah

IOCBF

(1)

1F4Bh

—

1F4Ch

—

1F4Dh

—

1F4Eh

ANSELC

1F4Fh

WPUC

1F50h

ODCONC

1F51h

SLRCONC

1F52h

INLVLC

1F53h

IOCCP

1F54h

IOCCN

1F55h

IOCCF

1F56h

1F6Fh

1F70h

1F7Fh

Common RAM

(Accesses

70h 7Fh)

Note 1: Available on PIC16F15243/44 only.

Legend:

Unimplemented data memory locations, read as '0'

Reserved

9.3

STATUS Register

The STATUS register contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the

destination for an instruction that affects the Z, DC or C bits, then writes to these three bits are disabled. These bits

are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the

result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUS will clear bits [4:3] and [1:0], and set the Z bit. This leaves the STATUS register as

‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS

register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits,

refer to the “Instruction Set Summary” chapter.

Important: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction.

PIC16F15213/14/23/24/43/44

Memory Organization

Preliminary Datasheet

DS40002195A-page 48

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