ASP00886IRGCR datasheet(5/139 Pages) TI

5 / 139 page

Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................2

4 Functional Block Diagrams............................................ 3

5 Revision History.............................................................. 6

6 Device Comparison......................................................... 9

6.1 Related Products........................................................ 9

7 Terminal Configuration and Functions........................10

7.1 Pin Diagrams............................................................ 10

7.2 Signal Descriptions................................................... 16

8 Specifications................................................................ 22

8.1 Absolute Maximum Ratings...................................... 22

8.2 ESD Ratings............................................................. 22

8.3 Recommended Operating Conditions.......................23

8.4 Active Mode Supply Current Into VCC Excluding

External Current.......................................................... 24

8.5 Low-Power Mode Supply Currents (Into VCC)

Excluding External Current..........................................25

8.6 Thermal Resistance Characteristics......................... 26

8.7 Schmitt-Trigger Inputs – General-Purpose I/O

(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to

P4.7, P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7,

P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)......................... 26

8.8 Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to

P2.7)............................................................................26

8.9 Leakage Current – General-Purpose I/O (P1.0 to

P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)

(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to

P8.2, PJ.0 to PJ.3, RST/NMI)......................................27

8.10 Outputs – General-Purpose I/O (Full Drive

Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to

P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7,

P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3).................... 27

8.11 Outputs – General-Purpose I/O (Reduced Drive

Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to

P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7,

P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3).................... 27

8.12 Output Frequency – General-Purpose I/O (P1.0

to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7,

P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to

P8.2, PJ.0 to PJ.3)...................................................... 28

8.13 Typical Characteristics – Outputs, Reduced

Drive Strength (PxDS.y = 0)........................................29

8.14 Typical Characteristics – Outputs, Full Drive

Strength (PxDS.y = 1)................................................. 30

8.15 Crystal Oscillator, XT1, Low-Frequency Mode........31

8.16 Crystal Oscillator, XT2............................................ 32

8.17 Internal Very-Low-Power Low-Frequency

Oscillator (VLO)...........................................................33

8.18 Internal Reference, Low-Frequency Oscillator

(REFO)........................................................................ 33

8.19 DCO Frequency...................................................... 34

8.20 PMM, Brownout Reset (BOR).................................35

8.21 PMM, Core Voltage.................................................35

8.22 PMM, SVS High Side..............................................35

8.23 PMM, SVM High Side............................................. 36

8.24 PMM, SVS Low Side...............................................36

8.25 PMM, SVM Low Side.............................................. 36

8.26 Wake-up Times From Low-Power Modes and

Reset........................................................................... 37

8.27 Timer_A...................................................................37

8.28 Timer_B...................................................................37

8.29 USCI (UART Mode) Clock Frequency.................... 38

8.30 USCI (UART Mode)................................................ 38

8.31 USCI (SPI Master Mode) Clock Frequency............ 39

8.32 USCI (SPI Master Mode)........................................ 39

8.33 USCI (SPI Slave Mode).......................................... 41

8.34 USCI (I2C Mode).....................................................43

8.35 12-Bit ADC, Power Supply and Input Range

Conditions................................................................... 44

8.36 12-Bit ADC, Timing Parameters..............................44

8.37 12-Bit ADC, Linearity Parameters Using an

External Reference Voltage or AVCC as

Reference Voltage.......................................................45

8.38 12-Bit ADC, Linearity Parameters Using the

Internal Reference Voltage..........................................45

8.39 12-Bit ADC, Temperature Sensor and Built-In

VMID ............................................................................ 46

8.40 REF, External Reference........................................ 47

8.41 REF, Built-In Reference.......................................... 47

8.42 Comparator_B.........................................................49

8.43 Ports PU.0 and PU.1...............................................49

8.44 USB Output Ports DP and DM................................51

8.45 USB Input Ports DP and DM...................................51

8.46 USB-PWR (USB Power System)............................ 51

8.47 USB-PLL (USB Phase-Locked Loop)..................... 52

8.48 Flash Memory......................................................... 52

8.49 JTAG and Spy-Bi-Wire Interface.............................52

9 Detailed Description......................................................53

9.1 CPU.......................................................................... 53

9.2 Operating Modes...................................................... 54

9.3 Interrupt Vector Addresses....................................... 55

9.4 Memory Organization................................................56

9.5 Bootloader (BSL)...................................................... 57

9.6 JTAG Operation........................................................ 58

9.7 Flash Memory........................................................... 59

9.8 RAM.......................................................................... 59

9.9 Peripherals................................................................59

9.10 Input/Output Diagrams............................................83

9.11 Device Descriptors (TLV)...................................... 107

10 Device and Documentation Support........................113

10.1 Getting Started and Next Steps............................ 113

10.2 Device Nomenclature............................................113

10.3 Tools and Software................................................115

10.4 Documentation Support........................................ 117

10.5 Related Links........................................................ 119

10.6 Support Resources............................................... 120

10.7 Trademarks...........................................................120

10.8 Electrostatic Discharge Caution............................120

10.9 Export Control Notice............................................120

10.10 Glossary..............................................................120

11 Mechanical, Packaging, and Orderable

Information.................................................................. 121

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