AS9C25512M2018L

AS9C25256M2018L

9/24/04, v.1.2

Alliance Semiconductor

P. 24 of 30

®

Notes:

2. Test conditions are specified using the load in the figure TAP AC output load equivalent.

TAP AC test conditions & output load equivalent

TAP DC electrical characteristics and operating conditions (VDD=2.5V ± 100 mV)

Description

Symbol

Min

Max

Units

Clock

Clock cycle time

100

-

ns

Clock frequency

-

10

MHz

Clock high time

40

-

ns

Clock low time

40

-

ns

Output Times

TCK low to TDO unknown

0

-

ns

TCK low to TDO valid

-20

ns

Setup Times

TMS/TDI setup

10

-

ns

Capture setup

10

-

ns

Hold Times

TMS/TDI hold

10

-

ns

Capture hold

10

-

ns

Reset Times

JTAG Reset

50

-

ns

JTAG Reset Recovery

50

-

ns

Description

Symbol

Conditions

Min

Max

Units

Input high (logic 1) voltage

1.7

VDD + 0.3

V

Input low (logic 0) voltage

-0.3

0.7

V

Input leakage current

0

10

µA

Output leakage current

10

µA

Output low voltage

0.2

V

Output low voltage

0.7

V

Output high voltage

2.1

V

Output high voltage

1.7

V

TDO

50

Ω

1.25V

20pF

Input pulse levels

Vss to 2.5V

Input rise and fall times

1V/ns

Input timing reference levels

1.25V

Output reference levels

1.25V

Test load termination supply voltage

1.25V