AS9C25512M2018L

AS9C25256M2018L

9/24/04, v.1.2

Alliance Semiconductor

P. 15 of 30

®

Notes:

1. Both Flow-through and Pipeline Outputs indicated. A particular port is configured in Flow-through mode if PL/FT for that port is driven low,

and in Pipeline mode if PL/FT is driven high or left unconnected.

3. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H).

Timings indicated for CE hold good for CE0 and CE1.

4. These cycles indicate that Counter works independent of all memory controls including R/W,CE and BEn.

5. If a Hold operation is performed for a Read access, the Data-out is held valid for the subsequent clock cycle also.

6. All timings are similar for both ports.

CLK

R/W

[Pipeline Mode]

[Flow-through Mode]

Write

(

Incr

A1

ADDRESS

A1

A1+1

A1+2

A1+2

A1+1

A1+2

A1+2

A2

A2+1

A2+1

A2

A1

D1

D1+1

D1+2

D1+2

Q1

Q1+1

Q3

Q4

Q1

Q1+1

Q4

DATA IN

RPT

INC

ADS

ADDRESS

INTERNAL

Hold

Rept

A2

Q1+2

Q1+2

Don’t care

Undefined

[4]

[5]

[5]

Load

Incr

Write

Write

Write

Read

Read

Read

Read

Incr

Incr

Hold

Load

(

Dsel

Dsel

Dsel

Dsel

Rept

Hold

Incr