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AS9C25512M2018L bảng dữ liệu(PDF) 19 Page - Alliance Semiconductor Corporation

tên linh kiện AS9C25512M2018L
Giải thích chi tiết về linh kiện  2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
PDF  30 Pages
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nhà sản xuất  ALSC [Alliance Semiconductor Corporation]
Trang chủ  https://www.alliancememory.com
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AS9C25512M2018L bảng dữ liệu(HTML) 19 Page - Alliance Semiconductor Corporation

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AS9C25512M2018L
AS9C25256M2018L
9/24/04, v.1.2
Alliance Semiconductor
P. 19 of 30
®
Collision timing waveform[2]
Notes:
1. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline mode of operation and can be different for different ports (Refer AC Timing characteristics).
2. Chip Selected (CE0 = L and CE1 =H). True for both ports.
3. Address indicated is the Internal Address used and is dependent on the Address counter control inputs for that cycle.
4. “Am” refers to matched address. “Aa” and “Ab” refer to any other valid address.
5. During address collision the data validity is guaranteed only if tCCO is greater than the minimum specified (Refer AC timing characteristics).
CLKA
ADDRESSA[3]
R/WA
Am
Aa
Am
Aa
Aa
Am
Aa
Am
Am
Am
Am
Aa
COLA
CLKB
ADDRESSB[3]
R/WB
Am
Ab
Am
Ab
Ab
Am
Ab
Am
Am
Am
Am
Ab
COLB
tCH[1]
tCYC[1]
tCL[1]
tWS
tAS
tAH
tCH[1]
tCL[1]
tCYC[1]
tAS
tAH
tWS
tWH
tCCO
tSCOL tRCOL
tSCOL
tRCOL
tWH
Don’t care
[5]
[4]
[4]



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