AS9C25512M2018L

AS9C25256M2018L

9/24/04, v.1.2

Alliance Semiconductor

P. 16 of 30

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Mailbox Interrupts

The AS9C25512M2018L/AS9C25256M2018L has an Inbuilt Mailbox Logic that can be used for communication between the two ports.

One memory location is assigned as mail box (message center) for each port. The location 7FFFE (HEX) is assigned as the message center

port B writes to memory location 7FFFE (HEX) (3FFFE for AS9C25256M2018L). The port A clears the interrupt flag by reading the

memory location 7FFFF (3FFFF for AS9C25256M2018L).(Refer Interrupt Logic Truth Table).

The interrupt flag is asserted in a flow-through mode (i.e., it follows the clock edge of the writing port). Also, the flag is reset in a flow-

through mode (i.e., it follows the clock edge of the reading port). Each port can read the other port’s mailbox without de-asserting the

interrupt and each port can write to its own mailbox without asserting the interrupt. If an application does not require message passing, INT

pins can be ignored.

Notes:

1. L = low, H = high, X = don't care

3. Address specified here is the internal address (refer Counter control truth table).

4. Both Interrupt Flags are De-asserted on power-up.

5. Interrupt feature is not supported in TQFP package.

6. Address A18 is a NC for AS9C25256M2018L, hence Interrupt addresses are 3FFFF and 3FFFE

Function

L to H

L

L

7FFFF

L to H

X

X

X

X

L

Assert Port B Interrupt Flag

L to H

X

X

X

L to H

H

L

7FFFF

X

H

De-assert Port B Interrupt Flag

L to H

X

X

X

L to H

L

L

7FFFE

L

X

Assert Port A Interrupt Flag

L to H

H

L

7FFFE

L to H

X

X

X

H

X

De-assert Port A Interrupt Flag