AS9C25512M2018L datasheet(17/30 Pages) ALSC

tên linh kiện	AS9C25512M2018L

Giải thích chi tiết về linh kiện	2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface

PDF	30 Pages

Scroll/Zoom	100%

nhà sản xuất	ALSC [Alliance Semiconductor Corporation]

Trang chủ	https://www.alliancememory.com

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17 / 30 page

AS9C25512M2018L

AS9C25256M2018L

9/24/04, v.1.2

Alliance Semiconductor

P. 17 of 30

Interrupt timing wave form[2]

Notes:

1. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline mode of operation and can be different for different ports (Refer AC Timing characteristics).

2. Chip Selected (CE0 = L and CE1 =H). True for both ports.

3. Address indicated is the Internal Address used and is dependent on the Address counter control inputs for that cycle.

4. 7FFFF (3FFFF for AS9C25256M2018L) is the Mailbox for port B and 7FFFE (3FFFE for AS9C25256M2018L) is the Mailbox for port A.

5. “Aa” and “Ab” refer to any other valid address other than 7FFFF or 7FFFE (3FFFF or 3FFFE for AS9C25256M2018L).

tCYC[1]

tCH[1]

tCL[1]

CLKA

R/WA[2]

tWS

tWH

tAS

tAH

INTA

ADDRESSA[3]

CLKB

R/WB[2]

ADDRESSB[3]

INTB

7FFFF

tWH

tWS

tCYC[1]

tCH[1]

tCL[1]

tSINT

tRINT

tSINT

tRINT

tAH

tAS

7FFFF

7FFFE

7FFFF

7FFFE

Don’t care

[4]

[5]

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