JS28F320J3A-150 datasheet(69/72 Pages) INTEL

69 / 72 page

256-Mbit J3 (x8/x16)

Datasheet

C.4

VCC, VPEN, RP# Transitions

Block erase, program, and lock-bit configuration are not guaranteed if VPEN or VCC falls outside of

the specified operating ranges, or RP#

≠ V

IH. If RP# transitions to VIL during block erase,

program, or lock-bit configuration, STS (in default mode) will remain low for a maximum time of

tPLPH + tPHRH until the reset operation is complete. Then, the operation will abort and the device

will enter reset/power-down mode. The aborted operation may leave data partially corrupted after

programming, or partially altered after an erase or lock-bit configuration. Therefore, block erase

and lock-bit configuration commands must be repeated after normal operation is restored. Device

power-off or RP# = VIL clears the Status Register.

The CUI latches commands issued by system software and is not altered by VPEN, CE0, CE1, or

CE2 transitions, or WSM actions. Its state is read array mode upon power-up, after exit from reset/

power-down mode, or after VCC transitions below VLKO. VCC must be kept at or above VPEN

during VCC transitions.

After block erase, program, or lock-bit configuration, even after VPEN transitions down to VPENLK,

the CUI must be placed in read array mode via the Read Array command if subsequent access to

the memory array is desired. VPEN must be kept at or below VCC during VPEN transitions.

C.5

Power Dissipation

When designing portable systems, designers must consider battery power consumption not only

during device operation, but also for data retention during system idle time. Flash memory’s

nonvolatility increases usable battery life because data is retained when system power is removed.

JS28F320J3A-150 bảng dữ liệu(PDF) 69 Page - Intel Corporation