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LPC5410X bảng dữ liệu(PDF) 68 Page - NXP Semiconductors |
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LPC5410X bảng dữ liệu(HTML) 68 Page - NXP Semiconductors |
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68 / 95 page ![]() LPC5410x All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved. Product data sheet Rev. 2.11 — 19 September 2019 68 of 95 NXP Semiconductors LPC5410x 32-bit ARM Cortex-M4/M0+ microcontroller [1] Based on characterization; not tested in production. 11.12 SCTimer/PWM output timing USART slave (in synchronous mode) 2.7V VDD 3.6 V tsu(D) data input set-up time CCLK = 1 MHz to 12 MHz 21 - ns CCLK = 48 MHz to 60 MHz 5 - ns CCLK = 96 MHz 4 - ns th(D) data input hold time CCLK = 1 MHz to 12 MHz 0 - ns CCLK = 48 MHz to 60 MHz 0 - ns CCLK = 96 MHz 0 - ns tv(Q) data output valid time CCLK = 1 MHz to 12 MHz 37 62 ns CCLK = 48 MHz to 60 MHz 22 25 ns CCLK = 96 MHz 19 21 ns Fig 23. USART timing Table 28. USART dynamic characteristics[1] Tamb = 40 C to 105 C; 1.62 V VDD 3.6 V; CL = 30 pF balanced loading on all pins; SLEW = standard mode. Parameters sampled at the 50% level of the falling or rising edge. Symbol Parameter Conditions Min Max Unit Un_SCLK (CLKPOL = 0) TXD RXD Tcy(clk) tsu(D) th(D) tv(Q) START BIT0 tvQ) Un_SCLK (CLKPOL = 1) START BIT0 BIT1 BIT1 aaa-015074 Table 29. SCTimer/PWM output dynamic characteristics Tamb = 40 C to 105 C; 1.62 V VDD 3.6 V CL = 30 pF. Simulated skew (over process, voltage, and temperature) of any two SCT fixed-pin output signals; sampled at 10 % and 90 % of the signal level; values guaranteed by design. Symbol Parameter Conditions Min Typ Max Unit tsk(o) output skew time - - - 3.0 ns |
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