LPC5410X datasheet(64/95 Pages) NXP

64 / 95 page

LPC5410x

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Product data sheet

Rev. 2.11 — 19 September 2019

64 of 95

NXP Semiconductors

LPC5410x

32-bit ARM Cortex-M4/M0+ microcontroller

11.10 SPI interfaces

The actual SPI bit rate depends on the delays introduced by the external trace, the

external device, system clock (CCLK), and capacitive loading. Excluding delays

introduced by external device and PCB, the maximum supported bit rate for SPI master

mode is 48 Mbit/s, and the maximum supported bit rate for SPI slave mode is 21 Mbit/s.

Table 27.

SPI dynamic characteristics[1]

Tamb = 40 C to 105 C; CL = 30 pF balanced loading on all pins; SLEW = standard mode. Parameters sampled at the 50 %

level of the rising or falling edge.

Symbol

Parameter

Conditions

Min

Max

Unit

SPI master 1.62V

 VDD  2.0 V

tDS

data set-up time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

tDH

data hold time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

tv(Q)

data output valid time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

SPI slave 1.62V

 VDD  2.0 V

tDS

data set-up time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

tDH

data hold time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

tv(Q)

data output valid time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

SPI master 2.7 V

 VDD  3.6 V

tDS

data set-up time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

tDH

data hold time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

tv(Q)

data output valid time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

SPI slave 2.7V

 VDD  3.6 V

tDS

data set-up time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

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