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LPC5410X bảng dữ liệu(PDF) 37 Page - NXP Semiconductors |
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LPC5410X bảng dữ liệu(HTML) 37 Page - NXP Semiconductors |
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37 / 95 page ![]() LPC5410x All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved. Product data sheet Rev. 2.11 — 19 September 2019 37 of 95 NXP Semiconductors LPC5410x 32-bit ARM Cortex-M4/M0+ microcontroller 7.22 Emulation and debugging Debug and trace functions are integrated into the ARM Cortex-M4 and ARM Cortex-M0+. Serial wire debug and trace functions are supported. The ARM Cortex-M4 is configured to support up to eight breakpoints and four watch points. The ARM Cortex-M0+ is configured to support up to four breakpoints and two watch points. In addition, JTAG boundary scan mode is provided. The ARM SYSREQ reset is supported and causes the processor to reset the peripherals, execute the boot code, restart from address 0x0000 0000, and break at the user entry point. The SWD pins are multiplexed with other digital I/O pins. On reset, the pins assume the SWD functions by default. |
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