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K32L3A bảng dữ liệu(PDF) 90 Page - NXP Semiconductors |
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K32L3A bảng dữ liệu(HTML) 90 Page - NXP Semiconductors |
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90 / 162 page ![]() 80% 20% 50% VIL Input Signal VIH Fall Time High Low Rise Time Midpoint1 The midpoint is VIL + (VIH - VIL) / 2 Figure 10. Input signal measurement reference All digital I/O switching characteristics, unless otherwise specified, assume that the output pins have the following characteristics. • CL=30 pF loads • Slew rate disabled • Normal drive strength 4.3.2 Nonswitching electrical specifications 4.3.2.1 Voltage and current operating requirements NOTE The term ‘VDDIO’ in the following table refers to the associated supply rail (either VDDIO1 or VDDIO2) of an input or output. Table 60. Voltage and current operating requirements Symbol Description Min. Max. Unit Notes VDD_DCDC(R UN) Supply of DCDC and AUXREG. 2.1 3.6 V VDD_CORE(R UN) Core and digital logic supply voltage for RUN mode 1.14 1.32 V 1 VDD_CORE(H SRUN) Core and digital logic supply voltage for HSRUN mode 1.33 1.47 V VDDIO1 Supply for Ports A, B, C, D and CORELDO 1.71 3.6 V VDDIO2 Supply for Port E 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V VDDIO – VDDA VDDIO-to-VDDA differential voltage –100 100 mV 2 VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V VIH Input high voltage Table continues on the next page... Electrical characteristics 90 K32L3A, Rev. 1, 09/2019 NXP Semiconductors |
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