K32L3A datasheet(39/162 Pages) NXP

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• Windowed, which is ideal for certain PWM zero-crossing-detection

applications

• Digitally Filtered

• Selectable performance levels: nano mode, normal mode, high speed mode

• Programmable hysteresis control

• Selectable inversion on comparator output

• External hysteresis can be used at the same time that the output filter is used for

internal functions

• Interrupt and DMA support

• Includes a 6-bit resolution DAC

• Selectable supply reference source for DAC

• Configurable low power mode or high speed mode for DAC

2.2.9 LPI2C

This device contains four LPI2C modules, which supports an efficient interface to an

I2C bus as a master and/or a slave. The LPI2C can continue operating in stop modes

provided an appropriate clock is available and is designed for low CPU overhead with

DMA offloading of FIFO register accesses. The LPI2C implements logic support for

standard-mode, fast-mode, fast-mode plus and ultra-fast modes of operation. The

LPI2C module also complies with the System Management Bus (SMBus)

Specification, version 2.

The LPI2C modules have the following features:

• Standard, Fast, Fast+ and Ultra Fast modes are supported

• High speed mode (HS) in slave mode

• High speed mode (HS) in master mode, if SCL pin implements current source

pull-up (device-specific)

• Multi-master support, including synchronization and arbitration. Multi-master

means any number of master nodes can be present. Additionally, master and slave

roles may be changed between messages (after a STOP is sent).

• Clock stretching: Sometimes multiple I2C nodes may be driving the lines at the

same time. If any I2C node is driving a line low, then that line will be low. I2C

nodes that are starting to transmit a logical one (by letting the line float high) can

Overview

K32L3A, Rev. 1, 09/2019

NXP Semiconductors

K32L3A bảng dữ liệu(PDF) 39 Page - NXP Semiconductors