K32L3A datasheet(40/162 Pages) NXP

40 / 162 page

detect that the line is low, and thereby know that another I2C node is active at the

same time.

• When node detection is used on the SCL line, it is called clock stretching, and

clock stretching is used as a I2C flow control mechanism for multiple laves.

• When node detection is used on the SDA line, it is called arbitration, and

arbitration ensures that there is only one I2C node transmitter at a time.

• General call, 7-bit and 10-bit addressing

• Software reset, START byte and Device ID (also require software support)

The LPI2C master supports:

• Command/transmit FIFO of 4words.

• Receive FIFO of 4words.

• Command FIFO will wait for idle I2C bus before initiating transfer

• Command FIFO can initiate (repeated) START and STOP conditions and one or

more master-receiver transfers

• STOP condition can be generated from command FIFO, or generated automatically

when the transmit FIFO is empty

• Host request input to control the start time of an I2C bus transfer

• Flexible receive data match can generate interrupt on data match and/or discard

unwanted data

• Flag and optional interrupt to signal Repeated START condition, STOP condition,

loss of arbitration, unexpected NACK, and command word errors

• Supports configurable bus idle timeout and pin-stuck-low timeout

The LPI2C slave supports:

• Separate I2C slave registers to minimize software overhead because of master/slave

switching

• Support for 7-bit or 10-bit addressing, address range, SMBus alert and general call

address

• Transmit data register that supports interrupt or DMA requests

• Receive data register that supports interrupt or DMA requests

• Software-controllable ACK or NACK, with optional clock stretching on ACK/

NACK bit

• Configurable clock stretching, to avoid transmit FIFO underrun and receive FIFO

overrun errors

• Flag and optional interrupt at end of packet, STOP condition, or bit error detection

Overview

K32L3A, Rev. 1, 09/2019

NXP Semiconductors

K32L3A bảng dữ liệu(PDF) 40 Page - NXP Semiconductors