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K32L3A bảng dữ liệu(PDF) 71 Page - NXP Semiconductors |
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K32L3A bảng dữ liệu(HTML) 71 Page - NXP Semiconductors |
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71 / 162 page ![]() Table 18. System signal descriptions (continued) Chip signal name Module signal name Description I/O VSSA — Analog ground I Table 19. EWM signal descriptions Chip signal name Module signal name Description I/O EWM_IN EWM_in EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low. I EWM_OUT_b EWM_out EWM reset out signal O Table 20. LLWU0 signal descriptions Chip signal name Module signal name Description I/O LLWU_Pn (n=[31:0] LLWU_Pn (n=[31:0] External Pin Wakeup inputs I 3.3.3 Memories and memory interfaces Table 21. FlexBus signal descriptions Chip signal name Module signal name Description I/O FB_CLKOUT FB_CLK FlexBus Clock Output O FB_A[23:16] FB_A[23:16] This is the address and data bus I/O FB_AD[31:0] FB_ADn This is the address and data bus, FB_AD. The number of byte lanes carrying the data is determined by the port size associated with the matching chip-select. The full 32-bit address is driven on the first clock of a bus cycle (address phase). After the first clock, the data is driven on the bus (data phase). During the data phase, the address is driven on the pins not used for data. For example, in 16-bit mode, the lower address is driven on FB_AD15–FB_AD0, and in 8-bit mode, the lower address is driven on FB_AD23–FB_AD0. I/O FB_CSn_b (n=[5:0]) FB_CSn (n=[5:0]) General Purpose Chip-Selects—Indicate which external memory or peripheral is selected. A particular chip-select is asserted when the transfer address is within the external memory's or peripheral's address space, as defined in CSAR[BA] and CSMR[BAM]. O Table continues on the next page... Pinouts K32L3A, Rev. 1, 09/2019 71 NXP Semiconductors |
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