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K32L3A bảng dữ liệu(PDF) 21 Page - NXP Semiconductors |
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K32L3A bảng dữ liệu(HTML) 21 Page - NXP Semiconductors |
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21 / 162 page  1. SR for reset related control and FF for power model related control 2. OFF for reset related control and FF for power model related control 3. It depends on MCU arbitration and SPM LPSEL/BGEN bit. 4. It depends on MCU arbitration and SPM LVDEN/BGEN/ALLREFN bit 5. It depends on MCU arbitration and SPM POREN bit. 6. It depends on MCU arbitration and SPM LPOEN/ALLREFN bit. 7. It depends on the configurations, see the next table for details. 8. Requires the VBAT supply to be properly powered. 9. It depends on SPM_CORELPCNFG[ALLREFEN] =1. 10. It depends on SPM_CORESC[VDDIOOVRIDE] = 1, SPM_CORELPCNFG[ALLREFEN] =1, and VDDIO2. The following tables list all power mode combinations and corresponding power behaviors. Table 8. MCU power mode combinations CM4F power mode1 CM0+ power mode2 Max CM4F core clock frequency Max CM0+ core clock frequency MCU power mode3 RUN RUN 48MHz 48MHz RUN RUN HSRUN 72MHz 72MHz HSRUN RUN VLPR 48MHz 48MHz RUN RUN VLPW 48MHz OFF RUN RUN VLPS 48MHz OFF RUN RUN STOP/PSTOP 48MHz OFF RUN RUN LLS 48MHz OFF RUN RUN VLLS 48MHz OFF RUN HSRUN RUN 72MHz 72MHz HSRUN HSRUN HSRUN 72MHz 72MHz HSRUN HSRUN VLPR 72MHz 72MHz HSRUN HSRUN VLPW 72MHz OFF HSRUN HSRUN VLPS 72MHz OFF HSRUN HSRUN STOP/PSTOP 72MHz OFF HSRUN HSRUN LLS 72MHz OFF HSRUN HSRUN VLLS 72MHz OFF HSRUN VLPR RUN 48MHz 48MHz RUN VLPR HSRUN 72MHz 72MHz HSRUN VLPR VLPR 8MHz 8MHz VLP VLPR VLPW 8MHz OFF VLP VLPR VLPS 8MHz OFF VLP VLPR STOP/PSTOP 48MHz OFF RUN VLPR LLS 8MHz OFF VLP VLPR VLLS 8MHz OFF VLP VLPW RUN OFF 48MHz RUN VLPW HSRUN OFF 72MHz HSRUN VLPW VLPR OFF 8MHz VLP Table continues on the next page... Overview K32L3A, Rev. 1, 09/2019 21 NXP Semiconductors |
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