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AX58200 bảng dữ liệu(PDF) 42 Page - ASIX Electronics Corporation |
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AX58200 bảng dữ liệu(HTML) 42 Page - ASIX Electronics Corporation |
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42 / 180 page ![]() 42 Copyright © 2019 ASIX Electronics Corporation. All rights reserved. AX58200 EtherCAT Slave Controller SoC 2.2.4 Power Modes and Wake-up Sources The AX58200 has power manager unit to support several operating modes for saving power. Table 2.2-2 lists all power modes in the AX58200. Mode CPU Operating Maximum Speed (MHz) LDO_CAP (V) Clock Disable Normal mode 160 1.20 All clocks are disabled by control register. Turbo mode 192 1.26 All clocks are disabled by control register. Idle mode CPU enter Sleep mode 1.20/1.26 Only CPU clock is disabled. Fast Wakeup Power- down mode (FWPD) CPU enters Deep Sleep mode 1.20/1.26 Most clocks are disabled except LIRC/LXT, and only RTC/WDT/Timer/UART peripheral clocks still enable if their clock sources are selected as LIRC/LXT. Normal Power-down mode (NPD) CPU enters Deep Sleep mode 1.20/1.26 Most clocks are disabled except LIRC/LXT, and only RTC/WDT/Timer/UART peripheral clocks still enable if their clock sources are selected as LIRC/LXT. Low leakage Power-down mode (LLPD) CPU enters Deep Sleep mode 0.9 Most clocks are disabled except LIRC/LXT, and only RTC/WDT/Timer/UART peripheral clocks still enable if their clock sources are selected as LIRC/LXT. Standby Power-down mode 0 (SPD0) [1] Power off Floating Only LIRC/LXT still enable for RTC function and wake-up timer usage Standby Power-down mode 1 (SPD1) [1] Power off Floating Only LIRC/LXT still enable for RTC function and wake-up timer usage Deep Power-down mode (DPD) Power off Floating Only LIRC/LXT still enable for RTC function and wake-up timer usage Table 2.2-2: Power Mode Table Note: [1] User must turn on LIRC before entering SPD0/1 mode. There are different power mode entry settings. Each power mode has different entry setting and leaving condition. Table 2.2-3 shows the entry setting for each power mode. When chip power-on, chip is running as normal mode. User can enter each mode by setting SLEEPDEEP (SCR[2]), PDEN (CLK_PWRCT:[7]) and PDMSEL (CLK_PMUCTL[2:0]) and execute WFI instruction. Table 2.2-3: Power Mode Difference Table Register/Instruction Mode SLEEPDEEP (SCR[2]) PDEN (CLK_PWRCTL[7]) PDMSEL (CLK_PMUCTL [2:0]) CPU Run WFI Instruction Normal mode 0 0 0 NO Idle mode 0 0 0 YES Fast Wakeup Power-down mode 1 1 2 YES Normal Power-down mode 1 1 0 YES Low leakage Power-down mode 1 1 1 YES Standby Power-down mode 0 1 1 4 YES Standby Power-down mode 1 1 1 5 YES Deep Power-down mode 1 1 6 YES |
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